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參數(shù)資料
| 型號(hào)： | L64388 |
| 廠商： | LSI Corporation |
| 英文描述： | A General-Purpose,High-Performance Remote Access Communications Processor(通用的、高性能、遠(yuǎn)程訪問通信處理器) |
| 中文描述： | 阿通用，高性能的遠(yuǎn)程訪問通信處理器（通用的，高性能，遠(yuǎn)程訪問通信處理器） |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 129K |
| 代理商： | L64388 |
4
L64388 Remote Access Processor (RAP) Chip
The Ethernet Interface contains a medium independent interface (MII) for
direct connection to an external PHY. This interface operates as either
half or full duplex. Its data transfer rate is either 10 Mbits (IEEE 802.3)
or 100 Mbits (IEEE 802.3u) media access control. It automatically retries
transmit frames when a collision occurs within the first 64 bytes. The
Ethernet interface incorporates 17 Remote Monitoring (RMON) statistics
counters to support network management.
The RAP chip contains four multiprotocol serial WAN interfaces These
interfaces support HDLC (high-level data link control), transparent, and
start/stop protocols. The maximum data rate is 52 Mbit/s for clocked
synchronous interfaces. The digital PLL (DPLL) for nonclocked
synchronous interfaces supports data rates up to 5.0 Mbits/s. The WAN
interfaces provide automatic baud rate detection for start/stop and clock
rate measurement for externally clocked synchronous lines. Line coding
for NRZ, NRZI, FM0, and FM1 is a programmable option. Figure 3 shows
the WAN port connectivities.
Figure 3 WAN Port Connectivity Options
The Peripheral Component Interconnect (PCI) interface complies with
PCI revision 2.1. The bus is 32 bits wide and transfers data at up to
33 MHz. It is compliant with PCI 5 V and 3.3 V signalling environments.
The RAP chip may be configured as either a PCI host or PCI satellite.
Additional LAN/WAN ports, multiple RAP chips, or server configurations
can connect to the PCI interface. As a PCI host, the RAP chip provides
an internal arbiter for glueless connection of up to two PCI satellites. In
either host or satellite mode, the RAP PCI interface acts as either a
master or a slave. It contains independent master and slave read and
RAP Chip
1 Ethernet to
4 Multiprotocol WAN
1 Ethernet to 2 ISDN BRI
Ethernet
Ethernet
SWC
SWC
SWC
RAP Chip
V.34
ISDN BRI
Multifunction Device
RAP Chip
V.34
ISDN BRI
SWC
Ethernet
SWC
ISDN BRI
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