62
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
Figure 6
L64118 256-Pin PBGA Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
B
CDE
F
G
HJ
K
L
M
N
P
R
T
U
V
W
Y
VSS
A
CLK
IR
TX
IRBL
GPIO48
GPIO45/
RCLK
CD
A
T
A[4]
TRST
GPIO43
CD
A
T
A[0]
SDET
A
VD[6]
A
VD[5]
A
VD[3]
TDI
RXD2
NC
A
VERRn
SC0_VPP_
ENn
NC
PLL
VDD
IREF
SA[1]
SA[4]
SA[6]
SA[9]
SBA[1]
SDQMH
SDQML
SBD[13]
SBD[9]
SBD[6]
SBD[3]
TTXREQ
CTSn0
NC
R
TSn0
RXD0
NC
A
VDD
ZTESTn
SA[2]
SA[5]
SA[8]
SBA[0]
SWEn
SBD[14]
SBD[12]
SBD[8]
SBD[5]
SBD[2]
TTXD
A
T
A
DTRn0
TCLK
CTSn1
PD
A
T
A_
DIR/OP_
MODE[2]
IRRX0
NC
A
VSS
SDCLK
SA[3]
SA[7]
SA[11]
SCASn
SBD[15]
SBD[11]
SBD[7]
SBD[4]
SBD[0]
DSRn0
NC
R
TSn1
GPIO42
NC
VSS
VDD
SA[0]
SA[10]
SRASn
VDD
SBD[10]
PLL
VSS
SBD[1]
VDD
TXD0
VSS
NC
TXD1
CERRn
ECLK
CV
ALID
CD
A
T
A[6]
CD
A
T
A[7]
CD
A
T
A[1]
CD
A
T
A[5]
CD
A
T
A[2]
CD
A
T
A[3]
VDD
CCLK
GPIO46
VSS
GPIO49
IDDTN
NC
SCLK
VDD
TXD2
TCK
OP_
MODE[0]
A
VD[7]
TMS
A
VD[4]
TDO
A
VD[2]
VSS
OP_
MODE[1]
A
VD[0]
VV
ALID
A
VD[1]
A
V
ALID
VDD
VREQn
AREQn
NC
SC0_
RSTn
SC0_
CLK
SC0_
DETECT
SC0_C4
SC0_C8
RXD1
NC
F
A
UL
Tn
B
USY
VDD
SELECT
A
CKn
PD
A
T
A[1]
PERR
OR
PD
A
T
A[0]
PD
A
T
A[2]
PD
A
T
A[3]
PD
A
T
A[4]
PD
A
T
A[5]
PD
A
T
A[6]
VSS
PD
A
T
A[7]
SELECT
-
INn
INITn
A
U
T
OFDn
STR
OBEn
SD
A
SCL
INTn4
VDD
INTn2
INTn1
INTn3
CSn2
INTn0
CSn1
CSn0
CSn4
CSn3
VSS
CSn5/
MEM-
STBn
CPU_CLK
BEn2
BEn3
RESETn
VDD
WRn
BEn0
BEn1
AD[30]
EA
CKn
ALE
RDn
AD[31]
VSS
NC
AD[26]
AD[28]
NC
VSS
SC0_
ENn
VCC_
VDD
SC1_IO
VSS
AD[8]
VDD
ADDR[1]
ADDR[5]
VSS
AD[23]
VDD
AD[29]
SC0_IO
SC1_
ENn
VPP_
SC1_CLK
AD[14]
AD[11]
AD[7]
AD[3]
AD[13]
AD[12]
AD[10]
AD[9]
AD[5]
AD[6]
AD[4]
AD[2]
AD[1]
AD[0]
ADDR[0]
ADDR[4]
ADDR[3]
ADDR[2]
ADDR[6]
ADDR[7]
AD[16]
AD[20]
AD[18]
AD[17]
AD[24]
AD[21]
AD[19]
AD[27]
AD[25]
AD[22]
SC1_
RSTn
SC1_
DETECT
SC1_
ENn
VCC_
AD[15]
IRRX1
118bds Page 62 Wednesday, February 3, 1999 12:37 PM