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參數(shù)資料
| 型號： | L64118 |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁數(shù)： | 22/68頁 |
| 文件大?。?/td> | 877K |
| 代理商： | L64118 |
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L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 29
Parallel Data Direction
Output
After reset, this signal serves as the PDATA_DIR output,
which controls the parallel data bus buffers for the 1284
PDATA[7:0] data lines. When the 1284 port is used as an
Aux port, this pin is driven HIGH.
RESETn
Asynchronous Reset
Input
Asserting this active LOW signal resets the L64118 to its
power on state. To ensure a complete reset of the
L64118, RESETn must be asserted for at least 16 SCLK
cycles.
Test Signals
These signals are for LSI Logic test purposes. They must be tied to a
constant value in normal operational mode.
ECLK
Connect to VSS
Input
This is an LSI Logic manufacturing test pin.
IDDTN
Connect to VSS
Input
This is an LSI Logic manufacturing test pin.
ZTESTn
Connect to VDD
Input
This is an LSI Logic manufacturing test pin. It is
deasserted HIGH for normal chip operation.
Serial Port/ICEPort
These signals connect the L64118 to an external modem, PC, terminal,
or other host that includes an RS232 interface. The L64118 contains
three serial ports that comply with the asynchronous specication of the
RS232 standard. The on-chip baud rate generators support the standard
bit rate for serial communication.
Three of the SIO1 signals can be congured to serve the internal ICEport
module.
CTSn0
Clear to Send Port 0
Input
When reset LOW, this signal indicates that the external
receiver is ready for data transfer through TxD0/RxD0. If
the Transmit Enable bit in the SIO Command register is
set HIGH when CTSn0 is reset LOW, data from the
Transmit register of Port 0 is serialized through TxD0.
118bds Page 29 Wednesday, February 3, 1999 12:37 PM
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