
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 27
CSn[3:0]
Programmable Chip Selects
Output
Each chip select pin can be programmed to assert in a
specic address area. These pins are used to select
specic external devices according to on-chip address
decoding. They make interfacing to various peripherals
easier, as they can remove the need for external address
decoders.
CSn[4]
Programmable Chip Select
Output
This pin is similar in function to the other ve chip select
output pins. It is used to select specic external devices
according to on-chip address decoding.
GPIO1
Bidirectional
CSn[4] can serve as a general-purpose I/O signal
(GPIO1) by setting bit 0 in the General-Purpose Mode
register.
CSn[5]/MEMSTBn
Chip Select[5] or Memory Strobe
Output
This pin is similar in function to the other ve chip select
output pins but holds the characteristic of being able to
function as the MEMSTBn (active LOW memory strobe)
signal. The MEMSTBn signal is a general-purpose
signal. It can be used to indicate that a memory
transaction is in progress. It is asserted in both read and
write cycles. The timing on this signal is programmable.
EACKn
Target Acknowledge
Input
This signal indicates to the L64118 that the external
device is ready to complete the current read or write
cycle. The transaction will nish if both EACKn is
asserted and the internal wait state generator has
expired. This mechanism allows devices to extend an
access beyond the number of wait states programmed for
that particular address area.
EACKn can be programmed to be either active HIGH or
LOW, using the XPOS bit in the CEBUSMODE register.
EACKn must be deasserted before the next transaction
acknowledge cycle.
For self-acknowledge devices, the external EACKn pin
can be ignored, so the transaction completes when the
wait state generator expires. This is controlled by the
XACK bit in the CECFGn register.
118bds Page 27 Wednesday, February 3, 1999 12:37 PM