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參數(shù)資料
| 型號： | L29S800F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8MEGABIT (1M】8 /512K】16) 3 VOLT CMOS FLASH MEMERY |
| 中文描述： | 8MEGABIT（100萬】8 / 16】為512k）3伏的CMOS閃存MEMERY |
| 文件頁數(shù)： | 17/54頁 |
| 文件大?。?/td> | 797K |
| 代理商： | L29S800F |
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L29S800F
PRELIMINARY
A
8MEGABIT (1M×8 /512K×16)
3 VOLT CMOS FLASH MEMERY
LinkSmart
17
071802
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As
such, manufacture and device codes must be accessible while the devices reside in the target system.
PROM programmers typically access the signature codes by raising A
9
to a high voltage. However,
multiplexing high voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the
command register. Following the command write, a read cycle from address XX00H retrieves the
manufacture code of 04H. A read cycle from address XX01H for x16(XX02H for x8) returns the device
code (L29S800F = DAH and 29S800F-B = 5BH for x8 mode; L29S800F = 22DAH and 29S800F-B =
225BH for x16 mode). (See Tables 4.1 and 4.2.) All manufacturer and device codes will exhibit odd
parity with DQ
7
defined as the parity bit. Sector state (protection or unprotection) will be informed by
address XX02H for x16 (XX04H for x8). Scanning the sector addresses (A
18
, A
17
, A
16
, A
15
, A
14
, A
13
,
and A
12
) while (A
6
, A
1
, A
0
) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected
sector. The programming verification should be perform margin mode on the protected sector. (See
Tables 2 and 3.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the
register, and also to write the Autoselect command during the operation, execute it after writing
Read/Reset command sequence.
Byte/Word Programming
The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus
cycle operation. There are two “unlock” write cycles. These are followed by the program set-up
command and data write cycles. Addresses are latched on the falling edge of
CE
or
WE
, whichever
happens later and the data is latched on the rising edge of
CE
or
WE
, whichever happens first. The
rising edge of
CE
or
WE
(whichever happens first) begins programming. Upon executing the
Embedded Program Algorithm command sequence, the system is not required to provide further
controls or timings. The device will automatically provide adequate internally generated program
pulses and verify the programmed cell margin.
The automatic programming operation is completed when the data on DQ
7
is equivalent to data written
to this bit at which time the devices return to the read mode and addresses are no longer latched. (See
Table 9, Hardware Sequence Flags.) Therefore, the devices require that a valid address to the devices
be supplied by the system at this particular instance of time. Hence,
Data
Polling must be performed
at the memory location which is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during
the programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot
be programmed back to a “1”. Attempting to do so may either hang up the device or result in an
apparent success according to the data polling algorithm but a read from read/reset mode will show
that the data is still “0”. Only erase operations can convert “0”s to “1”s.
Figure 20 illustrates the Embedded Program
TM
Algorithm using typical command strings and bus
operations.
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