參數(shù)資料
型號(hào): KSZ8893FQL
廠商: Micrel Inc
文件頁數(shù): 76/117頁
文件大小: 0K
描述: IC SWITCH FAST ETH 3PORT 128PQFP
標(biāo)準(zhǔn)包裝: 66
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: MII,RMII,SNI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
配用: 576-1603-ND - EVAL KIT EXPERIMENTAL KSZ8893MQL
其它名稱: 576-1565
Micrel, Inc.
KSZ8893FQL
October 2007
61
M9999-101607-1.3
Register 2 (0x02): Global Control 0
Bit
Name
R/W
Description
Default
7
New Back-off
Enable
R/W
New back-off algorithm designed for UNH
1 = Enable
0 = Disable
0
6-4
Reserved
R/W
Reserved
Do not change the default value.
100
3
Pass Flow Control
Packet
R/W
1 = Switch will not filter 802.1x “flow control” packets
0 = Switch will filter 802.1x “flow control” packets
0
2
Reserved
R/W
Reserved
Do not change the default value.
1
Reserved
R/W
Reserved
Do not change the default value.
0
Link Change Age
R/W
Link change from “l(fā)ink” to “no link” will cause fast aging (<800s)
to age address table faster. After an age cycle is complete, the
age logic will return to normal aging (about 200 sec).
1 = Enable
0 = Disable
Note: If any port is unplugged, all addresses will be automatically
aged out.
0
Register 3 (0x03): Global Control 1
Bit
Name
R/W
Description
Default
7
Pass All Frames
R/W
1 = Switch all packets including bad ones. Used solely for
debugging purposes. Works in conjunction with sniffer mode
only.
0
6
Reserved
R/W
Reserved
Do not change the default value.
0
5
IEEE 802.3x Transmit
Direction Flow Control
Enable
R/W
1 = Will enable transmit direction flow control feature.
0 = Will not enable transmit direction flow control feature. Switch
will not generate any flow control (PAUSE) frame.
1
4
IEEE 802.3x Receive
Direction Flow Control
Enable
R/W
1 = Will enable receive direction flow control feature.
0 = Will not enable receive direction flow control feature. Switch
will not react to any flow control (PAUSE) frame it receives.
1
3
Frame Length Field
Check
R/W
1 = Will check frame length field in the IEEE packets. If the actual
length does not match, the packet will be dropped (for
Length/Type field < 1500).
0
2
Aging Enable
R/W
1 = Enable age function in the chip
0 = Disable age function in the chip
Invert of
P2LED3 (pin
20) value
during reset
Note: P2LED3
has internal
pull-down.
1
Fast Age Enable
R/W
1 = Turn on fast age (800us)
0
Aggressive Back-off
Enable
R/W
1 = Enable more aggressive back off algorithm in half duplex
mode to enhance performance. This is not an IEEE standard.
0
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