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參數(shù)資料
| 型號(hào)： | KSZ8893FQL |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 55/117頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH FAST ETH 3PORT 128PQFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 控制器類型： | 以太網(wǎng)開關(guān)控制器 |
| 接口： | MII，RMII，SNI |
| 電源電壓： | 3.1 V ~ 3.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-PQFP（14x20） |
| 包裝： | 托盤 |
| 配用： | 576-1603-ND - EVAL KIT EXPERIMENTAL KSZ8893MQL |
| 其它名稱： | 576-1565 |
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Micrel, Inc.
KSZ8893FQL
October 2007
42
M9999-101607-1.3
SMI register access is the same as the MIIM register access, except for the register access requirements presented in
this section.
Repeater Mode
The KSZ8893FQL supports repeater mode in 100Base-TX Half Duplex mode. In repeater mode, all ingress packets are
broadcast to the other two ports. MAC address checking and learning are disabled.
Repeater mode is enabled by setting register 6 bit[7] to ‘1’. Prior to setting this bit, all three ports need to be configured
to 100Base-TX Half Duplex mode. Additionally, both PHY ports need to have auto-negotiation disabled.
The latency between the two PHY ports is 270 ns (minimum) and 310 ns (maximum). The 40 ns difference is one clock
skew (one 25 MHz clock period) between reception and transmission. Latency is defined as the time from the first bit of
the Destination Address (DA) entering the ingress port to the first bit of the DA exiting the egress port.
Advanced Switch Functions
Spanning Tree Support
To support spanning tree, port 3 is designated as the processor port.
The other ports (port 1 and port 2), can be configured in one of the five spanning tree states via “transmit enable”,
“receive enable” and “l(fā)earning disable” register settings in registers 18 and 34 for ports 1 and 2, respectively. The
following table shows the port setting and software actions taken for each of the five spanning tree states.
Disable State
Port Setting
Software Action
The port should not
forward or receive
any packets.
Learning is
disabled.
“transmit
enable = 0,
receive
enable = 0,
learning
disable =1”
The processor should not send any packets to the port. The switch may still send
specific packets to the processor (packets that match some entries in the “static
MAC table” with “overriding bit” set) and the processor should discard those
packets. Address learning is disabled on the port in this state.
Blocking State
Port Setting
Software Action
Only packets to the
processor are
forwarded.
Learning is
disabled.
“transmit
enable = 0,
receive
enable = 0,
learning
disable =1”
The processor should not send any packets to the port(s) in this state. The
processor should program the “Static MAC table” with the entries that it needs to
receive (for example, BPDU packets). The “overriding” bit should also be set so that
the switch will forward those specific packets to the processor. Address learning is
disabled on the port in this state.
Listening State
Port Setting
Software Action
Only packets to
and from the
processor are
forwarded.
Learning is
disabled.
“transmit
enable = 0,
receive
enable = 0,
learning
disable =1”
The processor should program the “Static MAC table” with the entries that it needs
to receive (for example, BPDU packets). The “overriding” bit should be set so that
the switch will forward those specific packets to the processor. The processor may
send packets to the port(s) in this state. See “Special Tagging Mode” for details.
Address learning is disabled on the port in this state.
Learning State
Port Setting
Software Action
Only packets to
and from the
processor are
forwarded.
Learning is
enabled.
“transmit
enable = 0,
receive
enable = 0,
learning
disable = 0”
The processor should program the “Static MAC table” with the entries that it needs
to receive (for example, BPDU packets). The “overriding” bit should be set so that
the switch will forward those specific packets to the processor. The processor may
send packets to the port(s) in this state. See “Special Tagging Mode” for details.
Address learning is enabled on the port in this state.
Forwarding State
Port Setting
Software Action
Packets are
forwarded and
received normally.
Learning is
enabled.
“transmit
enable = 1,
receive
enable = 1,
learning
disable = 0”
The processor programs the “Static MAC table” with the entries that it needs to
receive (for example, BPDU packets). The “overriding” bit is set so that the switch
forwards those specific packets to the processor. The processor can send packets
to the port(s) in this state. See “Special Tagging Mode” for details. Address learning
is enabled on the port in this state.
Table 14. Spanning Tree States
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8893FQL-EVAL | 功能描述:以太網(wǎng)開發(fā)工具 2+1 Port 10/100 Switch w/Tranceivers & Frame Buffers - Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| KSZ8893FQL-FX | 功能描述:以太網(wǎng) IC 2+1 Port 10/100 Switch w/Tranceivers & Frame Buffers, (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8893FQLI-FX | 功能描述:以太網(wǎng) IC 3-Port Ethernet Switch w MII/RMII Interface + 100FX (I-Temp, Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8893MBL | 功能描述:以太網(wǎng) IC 2+1 Port 10/100 Switch w/Tranceivers & Frame Buffers, 128-Ld PQFP(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8893MBL TR | 功能描述:以太網(wǎng) IC 2+1 Port 10/100 Switch w/Tranceivers & Frame Buffers, 100-Ball LFBGA (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
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