參數(shù)資料
型號: KSZ8873MLL
廠商: Micrel Inc
文件頁數(shù): 79/115頁
文件大小: 0K
描述: IC ETHERNET SWITCH 3PORT 64-LQFP
產(chǎn)品培訓(xùn)模塊: KSZ8873 Ethernet Switches
特色產(chǎn)品: KSZ8873 Ethernet Switch Controller
標(biāo)準(zhǔn)包裝: 160
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: MII
電源電壓: 1.8V,2.5V,3.3V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
其它名稱: 576-3459
Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
66
Revision 1.6
Register 23[6:0] (0x17): Port 1 Q1 Ingress Data Rate Limit
Register 39[6:0] (0x27): Port 2 Q1 Ingress Data Rate Limit
Register 55[6:0] (0x37): Port 3 Q1 Ingress Data Rate Limit
Bit
Name
R/W
Description
Default
7
Reserved
R/W
Reserved
Do not change the default values.
0
6-0
Q1 Ingress Data
Rate Limit
R/W
Ingress data rate limit for priority 1 frames
Ingress traffic from this priority queue is shaped according to the ingress
Data Rate Limit Table.
0
Register 24[6:0] (0x18): Port 1 Q2 Ingress Data Rate Limit
Register 40[6:0] (0x28): Port 2 Q2 Ingress Data Rate Limit
Register 56[6:0] (0x38): Port 3 Q2 Ingress Data Rate Limit
Bit
Name
R/W
Description
Default
7
Reserved
RO
Reserved
Do not change the default values.
0
6-0
Q2 Ingress Data
Rate Limit
R/W
Ingress data rate limit for priority 2 frames
Ingress traffic from this priority queue is shaped according to ingress Data
Rate Limit Table.
0
Register 25[6:0] (0x19): Port 1 Q3 Ingress Data Rate Limit
Register 41[6:0] (0x29): Port 2 Q3 Ingress Data Rate Limit
Register 57[6:0] (0x39): Port 3 Q3 Ingress Data Rate Limit
Bit
Name
R/W
Description
Default
7
Reserved
RO
Reserved
Do not change the default values.
0
6-0
Q3 Ingress Data
Rate Limit
R/W
Ingress data rate limit for priority 3 frames
Ingress traffic from this priority queue is shaped according to ingress Data
Rate Limit Table.
0
Note:
Most of the contents in registers 26-31 and registers 42-47 for ports 1 and 2, respectively, can also be accessed with the MIIM PHY registers.
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