參數資料
型號: KSZ8873MLL
廠商: Micrel Inc
文件頁數: 22/115頁
文件大?。?/td> 0K
描述: IC ETHERNET SWITCH 3PORT 64-LQFP
產品培訓模塊: KSZ8873 Ethernet Switches
特色產品: KSZ8873 Ethernet Switch Controller
標準包裝: 160
控制器類型: 以太網開關控制器
接口: MII
電源電壓: 1.8V,2.5V,3.3V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-LQFP(10x10)
包裝: 托盤
產品目錄頁面: 1081 (CN2011-ZH PDF)
其它名稱: 576-3459
Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
14
Revision 1.6
Pin Description and I/O Assignment (Continued)
Pin Number
Pin Name
Type
(1)
Description
26
SMTXC3/
REFCLKI_3
I/O
MLL/FLL: Switch MII transmit clock (MII modes only)
Output in PHY MII mode and SNI mode
Input in MAC MII and RMII mode.
RLL: Reference clock input
Note: pull-down by resistor is needed if internal reference clock is used in RLL by
register 198 bit 3.
27
SMTXER3/
MII_LINK_3
Ipd
Switch MII transmit error in MII mode
0= MII link indicator from host in MII PHY mode.
1= No link on port 3 MII PHY mode and enable By-pass mode.
28
SMRXDV3
lpu/O
Switch MII receive data valid
Strap option: MII mode selection
PU = PHY mode.
PD = MAC mode (In MAC mode, port 3 MII has to connect a powered active
external PHY for the normal operation)
29
SMRXD33/
REFCLKO_3
lpu/O
MLL/FLL: Switch MII receive data bit 3
RLL: Output reference clock in RMII mode.
Strap option: enable auto-negotiation on port 2 (P2ANEN)
PU = enable P2ANEN
PD = disable P2ANEN
30
SMRXD32
Ipu/O
Switch MII receive data bit 2
Strap option: Force the speed on port 2
PU = force port 2 to 100BT if P2ANEN = 0
PD = force port 2 to 10BT if P2ANEN = 0
31
SMRXD31
Ipu/O
Switch MII/RMII receive data bit 1
Strap option: Force duplex mode (P2DPX)
PU = port 2 default to full duplex mode if P2ANEN = 1 and auto-negotiation fails.
Force port 2 in full duplex mode if P2ANEN = 0.
PD = Port 2 set to half duplex mode if P2ANEN = 1 and auto-negotiation fails.
Force port 2 in half duplex mode if P2ANEN = 0.
32
GND
Gnd
Digital ground
33
SMRXD30
lpu/O
Switch MII/RMII receive data bit 0
Strap option: Force flow control on port 2 (P2FFC)
PU = always enable (force) port 2 flow control feature, regardless of Auto-
Negotiation result.
PD = port 2 flow control is enabled by auto- negotiation result.
34
SCRS3/
NC
Ipu/O
MLL/FLL: Switch MII carrier sense
RLL: No connection, Internal pull up.
Note: For MLL/FLL part, when chip is configured as MAC mode, this pin should be
driven from CRS pin of PHY or from CRS pin of FPGA with a logic of (TXEN |
RXDV). If only full duplex is used, then this pin should be pull-down by 1K resister.
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