參數(shù)資料
型號(hào): KSZ8873FLL
廠商: Micrel Inc
文件頁數(shù): 93/115頁
文件大?。?/td> 0K
描述: IC ETHERNET SW 3PORT 64LQFP
產(chǎn)品培訓(xùn)模塊: KSZ8873 Ethernet Switches
特色產(chǎn)品: KSZ8873 Ethernet Switch Controller
標(biāo)準(zhǔn)包裝: 160
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: MII
電源電壓: 1.8V,2.5V,3.3V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
其它名稱: 576-3631
KSZ8873FLL-ND
Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
79
Revision 1.6
Registers 118 to 120
Registers 118 to 120 are User Defined Registers (UDRs). These are general purpose read/write registers that can be
used to pass user defined control and status information between the KSZ8873 and the external processor.
Register 118 (0x76): User Defined Register 1
Bit
Name
R/W
Description
Default
7-0
UDR1
R/W
0x00
Register 119 (0x77): User Defined Register 2
Bit
Name
R/W
Description
Default
7-0
UDR2
R/W
0x00
Register 120 (0x78): User Defined Register 3
Bit
Name
R/W
Description
Default
7-0
UDR3
R/W
0x00
Registers 121 to 131
Registers 121 to 131 provide read and write access to the static MAC address table, VLAN table, dynamic MAC address
table, and MIB counters.
Register 121 (0x79): Indirect Access Control 0
Bit
Name
R/W
Description
Default
7-5
Reserved
R/W
Reserved
Do not change the default values.
000
4
Read High /
Write Low
R/W
=1, Read cycle
=0, Write cycle
0
3-2
Table Select
R/W
=00, Static MAC address table selected
=01, VLAN table selected
=10, Dynamic MAC address table selected
=11, MIB counter selected
00
1-0
Indirect
Address High
R/W
Bits [9:8] of indirect address
00
Register 122 (0x7A): Indirect Access Control 1
Bit
Name
R/W
Description
Default
7-0
Indirect
Address Low
R/W
Bits [7:0] of indirect address
0000_0000
Note:
A write to register 122 triggers the read/write command. Read or write access is determined by register 121 bit 4.
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