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參數(shù)資料
| 型號： | KSZ8873FLL |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 48/115頁 |
| 文件大小： | 0K |
| 描述： | IC ETHERNET SW 3PORT 64LQFP |
| 產(chǎn)品培訓(xùn)模塊： | KSZ8873 Ethernet Switches |
| 特色產(chǎn)品： | KSZ8873 Ethernet Switch Controller |
| 標準包裝： | 160 |
| 控制器類型： | 以太網(wǎng)開關(guān)控制器 |
| 接口： | MII |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
| 其它名稱： | 576-3631 KSZ8873FLL-ND |
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Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
38
Revision 1.6
802.1p Priority Field Re-Mapping is a QoS feature that allows the KSZ8873MLL/FLL/RLL to set the “User Priority
Ceiling” at any ingress port. If the ingress packet’s priority field has a higher priority value than the default tag’s priority
field of the ingress port, the packet’s priority field is replaced with the default tag’s priority field.
DiffServ-Based Priority
DiffServ-based priority uses the ToS registers (Registers 96 to 111) in the Advanced Control Registers section. The ToS
priority control registers implement a fully decoded, 64-bit Differentiated Services Code Point (DSCP) register to
determine packet priority from the 6-bit ToS field in the IP header. When the most significant 6 bits of the ToS field are
fully decoded, the resultant of the 64 possibilities is compared with the corresponding bits in the DSCP register to
determine priority.
Spanning Tree Support
To support spanning tree, port 3 is designated as the processor port.
The other ports (port 1 and port 2) can be configured in one of the five spanning tree states via “transmit enable”, “receive
enable” and “l(fā)earning disable” register settings in Registers 18 and 34 for ports 1 and 2, respectively. Table 12 shows the
port setting and software actions taken for each of the five spanning tree states.
Table 12. Spanning Tree States
Disable State
Port Setting
Software Action
The port should not forward or
receive any packets. Learning
is disabled.
“transmit enable =
0, receive enable
= 0, learning
disable =1”
The processor should not send any packets to the port. The switch may still
send specific packets to the processor (packets that match some entries in
the “static MAC table” with “overriding bit” set) and the processor should
discard those packets. Address learning is disabled on the port in this state.
Blocking State
Port Setting
Software Action
Only packets to the processor
are forwarded. Learning is
disabled.
“transmit enable =
0, receive enable
= 0, learning
disable =1”
The processor should not send any packets to the port(s) in this state. The
processor should program the “Static MAC table” with the entries that it
needs to receive (for example, BPDU packets). The “overriding” bit should
also be set so that the switch will forward those specific packets to the
processor. Address learning is disabled on the port in this state.
Listening State
Port Setting
Software Action
Only packets to and from the
processor are forwarded.
Learning is disabled.
“transmit enable =
0, receive enable
= 0, learning
disable =1”
The processor should program the “Static MAC table” with the entries that it
needs to receive (for example, BPDU packets). The “overriding” bit should
be set so that the switch will forward those specific packets to the processor.
The processor may send packets to the port(s) in this state. See “Tail
Tagging Mode” for details. Address learning is disabled on the port in this
state.
Learning State
Port Setting
Software Action
Only packets to and from the
processor are forwarded.
Learning is enabled.
“transmit enable =
0, receive enable
= 0, learning
disable = 0”
The processor should program the “Static MAC table” with the entries that it
needs to receive (for example, BPDU packets). The “overriding” bit should
be set so that the switch will forward those specific packets to the processor.
The processor may send packets to the port(s) in this state. See “Tail
Tagging Mode” for details. Address learning is enabled on the port in this
state.
Forwarding State
Port Setting
Software Action
Packets are forwarded and
received normally. Learning is
enabled.
“transmit enable =
1, receive enable
= 1, learning
disable = 0”
The processor programs the “Static MAC table” with the entries that it needs
to receive (for example, BPDU packets). The “overriding” bit is set so that
the switch forwards those specific packets to the processor. The processor
can send packets to the port(s) in this state. See “Tail Tagging Mode” for
details. Address learning is enabled on the port in this state.
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相關(guān)代理商/技術(shù)參數(shù) |
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| KSZ8873FLL-EVAL | 功能描述:以太網(wǎng)開發(fā)工具 3-Port Fast Ethernet Switch with 2x FX Ports - Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| KSZ8873FLLI | 功能描述:以太網(wǎng) IC 3-Port Fast Ethernet Switch with 2x FX Ports (Industrial Grade) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8873MLL | 功能描述:以太網(wǎng) IC 3-Port Fast Ethernet Switch with 1x MII Interface - Lead Free RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8873MLL AM | 功能描述:以太網(wǎng) IC 3-Port 10/100 Ethernet Switch with 1x MII Interface (Automotive Grade, Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8873MLL AM TR | 功能描述:以太網(wǎng) IC 3-Port 10/100 Ethernet Switch with 1x MII Interface (Automotive Grade, Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
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