參數(shù)資料
型號(hào): KSZ8873FLL
廠商: Micrel Inc
文件頁(yè)數(shù): 34/115頁(yè)
文件大?。?/td> 0K
描述: IC ETHERNET SW 3PORT 64LQFP
產(chǎn)品培訓(xùn)模塊: KSZ8873 Ethernet Switches
特色產(chǎn)品: KSZ8873 Ethernet Switch Controller
標(biāo)準(zhǔn)包裝: 160
控制器類型: 以太網(wǎng)開(kāi)關(guān)控制器
接口: MII
電源電壓: 1.8V,2.5V,3.3V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
其它名稱: 576-3631
KSZ8873FLL-ND
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Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
25
Revision 1.6
Functional Overview: Power Management
The KSZ8873MLL/FLL/RLL supports enhanced power management feature in low power state with energy detection to
ensure low-power dissipation during device idle periods. There are five operation modes under the power management
function which is controlled by two bits in Register 195 (0xC3) and one bit in Register 29 (0x1D),45(0x2D) as shown
below:
Register 195 bit[1:0] = 00 Normal Operation Mode
Register 195 bit[1:0] = 01 Energy Detect Mode
Register 195 bit[1:0] = 10 Soft Power-Down Mode
Register 195 bit[1:0] = 11 Power-Saving Mode
Register 29,45 bit 3 =1 Port-Based Power-Down Mode
Table 3 indicates all internal function blocks status under four different power management operation modes.
Table 3. Internal Function Block Status
KSZ8873MLL/FLL/RLL
Function Blocks
Power Management Operation Modes
Normal Mode
Power Saving Mode
Energy Detect Mode
Soft Power Down Mode
Internal PLL Clock
Enabled
Disabled
Tx/Rx PHY
Enabled
Rx unused block disabled
Energy detect at Rx
Disabled
MAC
Enabled
Disabled
Host Interface
Enabled
Disabled
Normal Operation Mode
This is the default setting bit[1:0]=00 in Register 195 after the chip power-up or hardware reset . When
KSZ8873MLL/FLL/RLL is in this normal operation mode, all PLL clocks are running, PHY and MAC are on and the host
interface is ready for CPU read or write.
During the normal operation mode, the host CPU can set the bit[1:0] in Register 195 to transit the current normal
operation mode to any one of the other three power management operation modes.
Energy-Detect Mode
The energy-detect mode provides a mechanism to save more power than in the normal operation mode when the
KSZ8873MLL/FLL/RLL is not connected to an active link partner. In this mode, the device will save up to 50% of the
power. If the cable is not plugged, the KSZ8873MLL/FLL/RLL can automatically enter to a low power state, a.k.a., the
energy-detect mode. In this mode, KSZ8873MLL/FLL/RLL will keep transmitting 120ns width pulses at 1 pulse/s rate.
Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8873MLL/FLL/RLL
can automatically power up to normal power state in energy detect mode.
Energy detect mode consists of two states, normal power state and low power state. While in low power state, the
KSZ8873MLL/FLL/RLL reduces power consumption by disabling all circuitry except the energy detect circuitry of the
receiver. The energy detect mode is entered by setting bit[1:0]=01 in Register 195. When the KSZ8873MLL/FLL/RLL is in
this mode, it will monitor the cable energy. If there is no energy on the cable for a time longer than pre-configured value at
bit[7:0]
Go-Sleep
time
in
Register
196,
KSZ8873MLL/FLL/RLL
will
go
into
a
low
power
state.
When
KSZ8873MLL/FLL/RLL is in low power state, it will keep monitoring the cable energy. Once the energy is detected from
the cable, KSZ8873MLL/FLL/RLL will enter normal power state. When KSZ8873MLL/FLL/RLL is at normal power state, it
is able to transmit or receive packet from the cable.
It will save about 87% of the power when MII interface is in PHY mode, Pin SMTXER3/MII_LINK_3 is connected to High,
Register 195 bit [1:0] =01, bit 2 =1(Disable PLL), not cables are connected.
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