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參數(shù)資料
| 型號： | KM44V1004D |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 4Bit CMOS Dynamic RAM with Extended Data Out(1M x 4位CMOS 動態(tài)RAM(帶擴(kuò)展數(shù)據(jù)輸出)) |
| 中文描述： | 100萬x 4位的擴(kuò)展數(shù)據(jù)輸出的CMOS動態(tài)RAM（3米× 4位的CMOS動態(tài)隨機(jī)存儲器（帶擴(kuò)展數(shù)據(jù)輸出）） |
| 文件頁數(shù)： | 8/22頁 |
| 文件大小： | 399K |
| 代理商： | KM44V1004D |
KM44C1004D, KM44V1004D
CMOS DRAM
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between
V
IH
(min) and V
IL
(max) and are assumed to be 2ns for all inputs.
Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max) can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
≥
t
RCD
(max).
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
oh
or V
ol
.
t
WCS
,
t
RWD
,
t
CWD
,
t
AWD
and
t
CPWD
are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If
t
WCS
≥
t
WCS
(min), the cycle is an early write cycle and the data output will remain high impedance for
the duration of the cycle. If
t
CWD
≥
t
CWD
(min),
t
RWD
≥
t
RWD
(min),
t
AWD
≥
t
AWD
(min) and
t
CPWD
≥
t
CPWD
(min) then the cycle is a
read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above con-
ditions is satisfied, the condition of the data out is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max) can be met.
t
RAD
(max) is specified as a reference point only.
If
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled by
t
AA
.
These specifiecations are applied in the test mode.
In test mode read cycle, the value of
t
RAC
,
t
AA
,
t
CAC
is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
t
CEZ(MAX)
,
t
REZ(MAX),
t
OEZ(MAX)
and
t
WEZ(MAX)
define the time at which the output achieves the open circuit condition and are
not referenced to output voltage level.
If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes
high before CAS high going, the open circuit condition of the output is achieved by RAS high going.
t
ASC
≥
6.0ns, Assume
t
T=2.0
ns.
If
t
RASS
≥
100us, then RAS precharge time must use
t
RPS
instead of
t
RP
.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 1024(1K) cycle of burst refresh must be executed within
16ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immedi-
ately before and after self refresh in order to meet refresh specification.
7.
6.
5.
10.
9.
8.
13.
12.
11.
14.
3.
2.
1.
4.
15.
16.
17.
18.
NOTES
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM44V4000AS-6 | 制造商:Samsung Electro-Mechanics 功能描述:Dynamic RAM, Fast Page, 4M x 4, 26 Pin, Plastic, TSOP |
| KM44V4000C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 4Bit CMOS Dynamic RAM with Fast Page Mode |
| KM44V4100AT-7 | 制造商:Samsung Semiconductor 功能描述: |
| KM44V4100C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 4Bit CMOS Dynamic RAM with Fast Page Mode |
| KM470M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:R. F. Molded Chokes |
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