參數(shù)資料
型號: KM4132G271BTQ(R)-10
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 128K x 32bit x 2 Banks Synchronous Graphic RAM LVTTL
中文描述: 128K的x 32位× 2銀行同步圖形RAM的LVTTL
文件頁數(shù): 31/51頁
文件大?。?/td> 1033K
代理商: KM4132G271BTQ(R)-10
KM4132G271B
CMOS SGRAM
- 31
Rev. 2.4 (May 1998)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Read & Write Cycle at Same Bank @Burst Length=4
HIGH
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] valid output data available after Row
enters precharge. Last valid output will be Hi-Z after
t
SHZ
from the clcok.
3. Access time from Row address.
t
CC
*(
t
RCD
+ CAS latency - 1) +
t
SAC
4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, & 8)
At Full page bit burst, burst is wrap-around.
*Note 1
t
RC
t
RCD
*Note 2
t
RDL
t
RDL
t
SHZ
*Note 4
t
SHZ
*Note 4
t
OH
Qa1
t
RAC
*Note 3
t
SAC
t
SAC
t
RAC
*Note 3
t
OH
A
9
A
8
(CL=2)
(CL=3)
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
Ra
Rb
Qa0
Qa2
Qa3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
Db0
Db1
Db2
Db3
Ra
Ca0
Rb
Cb0
WE
DSF
: Don
t care
Row Active
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
DQ
DQM
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