參數(shù)資料
型號: KFH1G16Q2M-DID6
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: CONN RCPT .100 100POS DL R/A AU
中文描述: 閃存(54MHz之間)
文件頁數(shù): 78/93頁
文件大?。?/td> 1219K
代理商: KFH1G16Q2M-DID6
OneNAND512/OneNAND1GDDP
FLASH MEMORY
78
AC CHARACTERISTICS
Synchronous Burst Read
Note
1. If OE is disabled before CE is disabled, the output will go to high-z by t
OEZ
(max. 17ns).
If CE is disabled before OE is disabled, the output will go to high-z by t
CEZ
(max. 20ns).
If CE and OE are disabled at the same time, the output will go to high-z by t
OEZ
(max. 17ns).
2. It is the following clock of address fetch clock.
Parameter
Symbol
KFG1216X2M/KFH1G16X2M
Unit
Min
Max
Clock
CLK
1
54
MHz
Clock Cycle
t
CLK
18.5
-
ns
Initial Access Time(at 54MHz)
t
IAA
-
88.5
ns
Burst Access Time Valid Clock to Output Delay
t
BA
-
14.5
ns
AVD Setup Time to CLK
t
AVDS
7
-
ns
AVD Hold Time from CLK
t
AVDH
7
-
ns
Address Setup Time to CLK
t
ACS
7
-
ns
Address Hold Time from CLK
t
ACH
7
-
ns
Data Hold Time from Next Clock Cycle
t
BDH
4
-
ns
Output Enable to Data
t
OE
-
20
ns
CE Disable to Output High Z
t
CEZ
1)
-
20
ns
OE Disable to Output High Z
t
OEZ
1)
-
17
ns
CE Setup Time to CLK
t
CES
7
-
ns
CLK High or Low Time
t
CLKH/L
t
CLK
/3
-
ns
CLK
2)
to RDY valid
t
RDYO
-
14.5
ns
CLK to RDY Setup Time
t
RDYA
-
14.5
ns
RDY Setup Time to CLK
t
RDYS
4
-
ns
CE low to RDY valid
t
CER
-
15
ns
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