參數(shù)資料
型號: KFH1G16Q2M-DID5
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: FLASH MEMORY(54MHz)
中文描述: 閃存(54MHz之間)
文件頁數(shù): 4/93頁
文件大?。?/td> 1219K
代理商: KFH1G16Q2M-DID5
OneNAND512/OneNAND1GDDP
FLASH MEMORY
4
Document Title
OneNAND
Revision History
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
Revision No.
0.4
1.0
1.1
1.2
Remark
Preliminary
Final
Final
Draft Date
June 22, 2004
August 5, 2004
August 26, 2004
October 26, 2004
History
1. Corrected the errata
2. Added spare assignment information in detail
3. Added NAND array memory map
4. Added manufacturer ID for CS as 00ECh
5. Added stepping ID for CS in version ID register
6. Divided default status of interrupt status register by Warm,Hot reset and
Cold reset
7. Revised Load operation flow chart
8. Revised Program operation flow chart
9. Deleted DBS setting step in Copy-back operation
10. Added OTP description
11. Revised OTP Load and Program flow chart
12. Added INT guidance
13. ECC description is revised
14. Added Data Protection Scheme during Power-down
15. Added DC/AC parameters
1. Deleted 2.7V product
2. Added 2.65V product
3. Added 3.3V product and industrial temperature in 3.3V product
4. Deleted Unlock/Lock BootRAM command
5. Added DBS setting step in Copy-back operation
6. Added 2.65V/3.3V DC parameters
7. Revised tCES from 9ns to 7ns
8. Deleted tOEH in asynchronous read operation
9. Revised NOP from 4 times per each main and spare in a page to 2 times
per sector
10. Revised Write Protection status description
11. Added DDP selection and operation guidance
12. Added 1Gb DDP device ID
13. Added INT bit status in Cold Reset operation
14. Moved Interrupt register setting before inputting command in all flow
charts
15. Revised Dual operation diagrams
16. Added and revised the asynchronous read operation timing diagram
17. Revised the asynchronous write operation timing diagram
18. Added the tREADY parameter in Hot Reset operation
1. Revised standby current for DDP
1. Corrected DDP device ID
2. Excluded Commercial Temperature range
3. Revised Cold Reset timing diagram
4. Added CE and RDY in Warm Reset diagram
5. Excluded Write while Load and Read while Program operation
6. Revised Extended Temperature minimum value from -25 to -30
7. Revised typical tOTP, tLOCK from 300us to 600us
8. Revised max tOTP, tLOCK from 600us to 1000us
9. Revised Icc4, Icc5 test condition
10. Added Endurance and Data Retention
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