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參數(shù)資料
| 型號(hào)： | K9F4008W0A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512K x 8 bit NAND Flash Memory |
| 中文描述： | 為512k × 8位NAND快閃記憶體 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 318K |
| 代理商： | K9F4008W0A |
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
4
PRODUCT INTRODUCTION
The K9F4008W0A is a 4M bit memory organized as 4096 rows by 1024 columns. A 256-bit data register is connected to memory cell
arrays accommodating data transfer between the registers and the cell array during frame read and frame program operations. The
memory array is composed of unit NAND structures in which 8 cells are connected serially.
Each of the 8 cells reside in a different row. A block consists of the 32 rows, totaling 4096 unit NAND structures of 8bits each. The
array organization is shown in Figure 2. The program and read operations are executed on a frame basis, while the erase operation is
executed on a block basis. The memory array consists of 128 separately erasable 4K-byte blocks.
The K9F4008W0A has addresses multiplexed into 8 I/O pins. This scheme not only reduces pin count but allows systems upgrades to
higher density flash memories by maintaining consistency in system board design. Command, address and data are all written
through I/O
′
s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and
Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus
cycle except for Block Erase command which requires two cycles. For byte-level addressing, the 512K byte physical space requires a
19-bit address, low row address and high row address. Frame Read and frame Program require the same three address cycles fol-
lowing by a command input. In the Block Erase operation, however, only the two row address cycles are required.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the K9F4008W0A.
Table 1. COMMAND SETS
Caution
: Any undefined command inputs are prohibited except for above command set of Table 1.
Function
1st. Cycle
2nd. Cycle
Acceptable Command during Busy
Read
00h
-
Reset
FFh
-
O
Frame Program
80h
10h
Block Erase
60h
D0h
Status read
70h
-
O
Read ID
90h
-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K9F4008W0A- | 512K x 8 bit NAND Flash Memory |
| K9F4008W0A-TCB0 | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVPS00; No. of Contacts:37; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight |
| K9F4008W0A-TIB0 | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVPS00; No. of Contacts:37; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight |
| K9F4G08U0M | 512M x 8 Bits / 1G x 8 Bits NAND Flash Memory |
| K9K8G08U1M | 512M x 8 Bits / 1G x 8 Bits NAND Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K9F4008W0A- | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512K x 8 bit NAND Flash Memory |
| K9F4008W0A-TCB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512K x 8 bit NAND Flash Memory |
| K9F4008W0A-TIB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512K x 8 bit NAND Flash Memory |
| K9F4G08U0A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY |
| K9F4G08U0A-I | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY |
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