參數(shù)資料
型號(hào)： K4N26323AE
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 128Mbit GDDR2 SDRAM
中文描述： 128Mbit GDDR2 SDRAM的
文件頁(yè)數(shù)： 10/52頁(yè)
文件大?。?/td> 826K
代理商： K4N26323AE
- 10 -
Rev. 1.7 (Jan. 2003)
128M GDDR2 SDRAM
K4N26323AE-GC
Power-Up Sequence
GDDR2 SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Power Up Sequence
- Apply Power and Keep CKE at low state. (All other inputs may be undefined)
- Apply VDD before VDDQ.
- Apply VDDQ before VREF.
- Start low frequency clock
(100MHz)
and maintain stable condition for minimum 200us.
- The minimum of 200us after stable power and clock (CK, /CK), apply NOP and take CKE to be high.
- Issue precharge command for all banks of the device ( tS/tH =0.5tCK).
- Issue EMRS command to initialize DRAM with DLL OFF and On-die Termination OFF( tS/tH=0.5tCK) .
- Issue EMRS command to control DLL and decide on-die termination state.
Within 100 clocks after issuing EMRS command for DLL on, stable high frequency clock should be supplied to DRAM.
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
(V=Valid value)
- The additional 1ms clock cycles are required to lock the DLL and determine value of on-die termination after issuing
EMRS command or supplying stable clock from a controller.
Apply NOP during Locking DLL to protect invalid command.
- Issue precharge command for all banks of the device.
- Issue EMRS command
- Issue at least 10 or more Auto refresh command to update the value of on-die termination.
- Issue a MRS command to initialize the mode register.
- Issue any command.
Power up & Initialization Sequence
CMD
tRP
CK,
CK
~
CKE
all banks
NOP
1st Auto
10th Auto
tRFC
MRS
4 Clock min.
Any
1ms
200 us
EMRS
2
< 100tCK
stable high freq.
NOP
* Minimum setup/hold time tIS, tIHmin = 0.5tCK at the Low frequency without DLL
* Within 100 tCK after issuing EMRS2, PLL(DLL) of controller should be enabled.
* During changing clock frequency, the changing rate should be smaller than 100ps/30tCK
low freq. (> 100Mhz)
EMRS
1
NOP
NOP
EMRS
all banks
tRP
tMRD
Address Bus
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
0
1
0
X
X
0
X
0
0
X
Extended Mode
Register
Address Bus
A
4
A
3
A
2
A
1
A
0
0
1
0
V
V
1
V
V
V
V
Extended Mode
Register
tRFC
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