參數(shù)資料
型號: K4M64163PK-BE900
元件分類: DRAM
英文描述: 4M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54
封裝: LEAD FREE, FBGA-54
文件頁數(shù): 11/12頁
文件大小: 114K
代理商: K4M64163PK-BE900
K4M64163PK - R(B)E/G/C/F
October 2005
8
Mobile-SDRAM
AC CHARACTERISTICS(AC operating conditions unless otherwise noted)
NOTES :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Parameter
Symbol
-75
-90
-1L
Unit
Note
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS latency=3
tCC
7.5
1000
9
1000
9
1000
ns
1
CAS latency=2
tCC
12
15
CAS latency=1
tCC
-
25
CLK to valid output delay
CAS latency=3
tSAC
6
7
ns
1,2
CAS latency=2
tSAC
9
10
CAS latency=1
tSAC
-
20
Output data hold time
CAS latency=3
tOH
2.5
ns
2
CAS latency=2
tOH
2.5
CAS latency=1
tOH
-
2.5
CLK high pulse width
tCH
2.5
3.0
ns
3
CLK low pulse width
tCL
2.5
3.0
ns
3
Input setup time
tSS
2.0
ns
3
Input hold time
tSH
1
ns
3
CLK to output in Low-Z
tSLZ
1
ns
2
CLK to output in Hi-Z
CAS latency=3
tSHZ
6
7
ns
CAS latency=2
9
10
CAS latency=1
-
20
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