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參數(shù)資料
| 型號： | ISPPAC-CLK5308S-01TN48C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 30/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUFFER FANOUT 8OUTPUT 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | ispClock™ |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送，零延遲緩沖器 |
| PLL： | 帶旁路 |
| 輸入： | HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL |
| 輸出： | eHSTL，HSTL，LVCMOS，LVTTL，SSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:8 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 267MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
| 其它名稱： | 220-1000 |
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Lattice Semiconductor
ispClock5300S Family Data Sheet
36
Evaluation Fixture
Included in the basic ispClock5300S Design Kit is an engineering prototype board that can be connected to the
parallel port of a PC using a Lattice ispDOWNLOAD
cable. It demonstrates proper layout techniques for the
ispClock5300S and can be used in real time to check circuit operation as part of the design process. Input and out-
put connections (SMA connectors for all RF signals) are provided to aid in the evaluation of the ispClock5300S for
a given application. (Figure 31).
Figure 31. Download from a PC
IEEE Standard 1149.1 Interface (JTAG)
Serial Port Programming Interface Communication with the ispClock5300S is facilitated via an IEEE 1149.1 test
access port (TAP). It is used by the ispClock5300S both as a serial programming interface, and for boundary scan
test purposes. A brief description of the ispClock5300S JTAG interface follows. For complete details of the refer-
ence specication, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std.
1149.1-1990 (which now includes IEEE Std. 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the
ispClock5300S. The TAP controller is a state machine driven with mode and clock inputs. Given in the correct
sequence, instructions are shifted into an instruction register which then determines subsequent data input, data
output, and related operations. Device programming is performed by addressing the conguration register, shifting
data in, and then executing a program conguration instruction, after which the data is transferred to internal
E
2CMOS cells. It is these non-volatile cells that store the conguration of the ispClock5300S. A set of instructions
are dened that access all data registers and perform other internal control operations. For compatibility between
compliant devices, two data registers are mandated by the IEEE 1149.1 specication. Others are functionally spec-
ied, but inclusion is strictly optional. Finally, there are provisions for optional data registers dened by the manu-
facturer. The two required registers are the bypass and boundary-scan registers. Figure 32 shows how the
instruction and various data registers are organized in an ispClock5300S.
Part Number
Description
PAC-SYSTEMCLK5312S
Complete system kit, evaluation board, ispDOWNLOAD cable and software.
ispDownload
Cable (6')
4
Other
System
Circuitry
ispClock5300S
Device
PAC-Designer
Software
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5308S-01TN48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ispPAC-CLK5308S-01TN48I | 功能描述:時(shí)鐘驅(qū)動器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5308S-01TN48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5308S-01TN64C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5308S-01TN64I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
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