參數(shù)資料
型號: ISP1583ET2
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, MO-195, SOT543-1,TFBGA-64
文件頁數(shù): 4/100頁
文件大?。?/td> 508K
代理商: ISP1583ET2
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
10 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
DATA10
48
A10
A8
I/O
bit 10 of the bidirectional data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
DATA11
49
A9
C4
I/O
bit 11 of the bidirectional data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
DATA12
50
B8
B7
I/O
bit 12 of the bidirectional data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
DATA13
51
A8
A7
I/O
bit 13 of the bidirectional data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
DATA14
52
B7
C6
I/O
bit 14 of the bidirectional data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
DATA15
53
A7
C5
I/O
bit 15 of the bidirectional data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
54
B6
-
I/O pad supply voltage (1.65 V to 3.6 V); see Section 8.16
VBUS
55
B5
A6
A
USB bus power sensing input — Used to detect
whether the host is connected or not; connect a 1
F
electrolytic or tantalum capacitor and a 1 M
pull-down
resistor to ground; see Section 8.14
VBUS pulsing output — In OTG mode; connect a 1 F
electrolytic or tantalum capacitor and a 1 M
pull-down
resistor to ground; see Section 8.14
5 V tolerant
VCC1V8[4] 56
A6
B5
-
voltage regulator output (1.8 V
± 0.15 V); tapped out
voltage from the internal regulator; this regulated voltage
cannot drive external devices; decouple this pin using
4.7
F and 0.1 F capacitors; see Section 8.16
XTAL2
57
A5
O
crystal oscillator output (12 MHz); connect a fundamental
parallel-resonant crystal; leave this pin open when using
an external clock source on pin XTAL1; see Table 100
XTAL1
58
A4
I
crystal oscillator input (12 MHz); connect a fundamental
parallel-resonant crystal or an external clock source
(leaving pin XTAL2 unconnected); see Table 100
DGND
59
B4
-
digital ground
MODE0/
DA1[3]
60
A3
C2
I/O
Mode selection input 0 — Selects the read/write strobe
functionality in generic processor mode during power-up:
LOW: for the Freescale mode; the function of pin 19 is
RW_N and pin 20 is DS_N
HIGH (connect to VCC(I/O)): for the 8051 mode; the
function of pin 19 is RD_N and pin 20 is WR_N
Address selection output — Selects the Task File
register of an ATA/ATAPI device during normal operation;
bidirectional pad; 10 ns slew-rate control; TTL; 5 V tolerant
61
B3
-
regulator supply voltage (3.3 V
± 0.3 V); this pin supplies
the internal regulator; see Section 8.16
Table 3.
Pin description …continued
Symbol[1]
Pin
Type[2] Description
ISP1583BS ISP1583ET;
ISP1583ET2
ISP1583ET1
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