參數(shù)資料
型號: ISP1583ET2
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, MO-195, SOT543-1,TFBGA-64
文件頁數(shù): 33/100頁
文件大?。?/td> 508K
代理商: ISP1583ET2
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
37 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Table 32.
Interrupt Enable register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
IEP7TX
IEP7RX
Reset
-
----
0
Bus reset
-
----
0
Access
-
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
IEP6TX
IEP6RX
IEP5TX
IEP5RX
IEP4TX
IEP4RX
IEP3TX
IEP3RX
Reset
0
0000
0
Bus reset
0
0000
0
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
IEP2TX
IEP2RX
IEP1TX
IEP1RX
IEP0TX
IEP0RX
reserved
IEP0SETUP
Reset
0
0000
-
0
Bus reset
0
0000
-
0
Access
R/W
-
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
IEVBUS
IEDMA
IEHS_STA
IERESM
IESUSP
IEPSOF
IESOF
IEBRST
Reset
0
0000
0
Bus reset
0
0000
0
1
Access
R/W
Table 33.
Interrupt Enable register: bit description
Bit
Symbol
Description
31 to 26
-
reserved
25
IEP7TX
Logic 1 enables interrupt from the indicated endpoint.
24
IEP7RX
Logic 1 enables interrupt from the indicated endpoint.
23
IEP6TX
Logic 1 enables interrupt from the indicated endpoint.
22
IEP6RX
Logic 1 enables interrupt from the indicated endpoint.
21
IEP5TX
Logic 1 enables interrupt from the indicated endpoint.
20
IEP5RX
Logic 1 enables interrupt from the indicated endpoint.
19
IEP4TX
Logic 1 enables interrupt from the indicated endpoint.
18
IEP4RX
Logic 1 enables interrupt from the indicated endpoint.
17
IEP3TX
Logic 1 enables interrupt from the indicated endpoint.
16
IEP3RX
Logic 1 enables interrupt from the indicated endpoint.
15
IEP2TX
Logic 1 enables interrupt from the indicated endpoint.
14
IEP2RX
Logic 1 enables interrupt from the indicated endpoint.
13
IEP1TX
Logic 1 enables interrupt from the indicated endpoint.
12
IEP1RX
Logic 1 enables interrupt from the indicated endpoint.
11
IEP0TX
Logic 1 enables interrupt from control IN endpoint 0.
10
IEP0RX
Logic 1 enables interrupt from control OUT endpoint 0.
9
-
reserved
8
IEP0SETUP
Logic 1 enables interrupt for the set-up data received on endpoint 0.
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