參數(shù)資料
型號： ISP1583ET2
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, MO-195, SOT543-1,TFBGA-64
文件頁數(shù)： 39/100頁
文件大?。?/td> 508K
代理商： ISP1583ET2
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
42 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Example 1: Consider that the transfer size is 512 bytes and the MaxPacketSize is
programmed as 64 bytes, the Buffer Length register need not be lled. This is because the
transfer size is a multiple of MaxPacketSize, and MaxPacketSize packets will be
automatically validated because the last packet is also of MaxPacketSize.
Example 2: Consider that the transfer size is 510 bytes and the MaxPacketSize is
programmed as 64 bytes, the Buffer Length register must be lled with 62 bytes just
before the microprocessor writes the last packet of 62 bytes. This ensures that the last
packet, which is a short packet of 62 bytes, is automatically validated.
Use bit VENDP in the Control register if you are not using the Buffer Length register.
This is applicable only to PIO mode access.
OUT endpoint: The DATACOUNT value is automatically initialized to the number of data
bytes sent by the host on each ACK.
Remark: When using a 16-bit microprocessor bus, the last byte of an odd-sized packet is
output as the lower byte (LSByte).
Remark: Buffer Length is valid only after an interrupt is generated for the OUT endpoint.
9.3.5 Buffer Status register (address: 1Eh)
This register is accessed using index. The endpoint index must rst be set before
accessing this register for the corresponding endpoint. It reects the status of the double
buffered endpoint FIFO.
Remark: This register is not applicable to the control endpoint.
Remark: For endpoint IN data transfer, rmware must ensure a 200 ns delay between
writing of the data packet and reading the Buffer Status register. For endpoint OUT data
transfer, rmware must also ensure a 200 ns delay between receiving the endpoint
interrupt and reading the Buffer Status register. For more information, refer to Ref. 3
Table 41.
Buffer Length register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
DATACOUNT[15:8]
Reset
00000000
Bus reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
DATACOUNT[7:0]
Reset
00000000
Bus reset
00000000
Access
R/W
Table 42.
Buffer Length register: bit description
Bit
Symbol
Description
15 to 0
DATACOUNT[15:0]
Data Count: Determines the current packet size of the indexed
endpoint FIFO.
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ISP1583ET2,518 功能描述:外圍驅(qū)動器與原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
ISP1583ET2-T 功能描述:外圍驅(qū)動器與原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
ISP1583ET-T 功能描述:外圍驅(qū)動器與原件 - PCI HI-SPEED USB2 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
ISP1583ETUM 功能描述:IC USB CTRL HI-SPEED 64TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
ISP166 功能描述:機(jī)架和機(jī)柜配件 PANELS 1600HX600D RoHS:否 制造商:Bivar 產(chǎn)品:Rack Accessories 面板空間: 顏色:Black
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