參數(shù)資料
型號(hào)： ISP1583BS,551
廠商： ST-ERICSSON
元件分類(lèi)： 總線(xiàn)控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝： 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁(yè)數(shù)： 54/100頁(yè)
文件大?。?/td> 508K
代理商： ISP1583BS,551
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
56 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
9.4.6 DMA Interrupt Reason register (address: 50h)
This 2-byte register shows the source(s) of DMA interrupt. Each bit is refreshed after a
DMA command is executed. An interrupt source is cleared by writing logic 1 to the
corresponding bit. On detecting the interrupt, the external microprocessor must read the
DMA Interrupt Reason register and mask it with the corresponding bits in the DMA
Interrupt Enable register to determine the source of the interrupt.
The bit allocation is given in Table 72.
Table 72.
DMA Interrupt Reason register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
TEST3
reserved
GDMA_
STOP
EXT_EOT
INT_EOT
INTRQ_
PENDING
DMA_
XFER_OK
Reset
0
-
00000
Bus reset
0
-
00000
Access
R
-
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
READ_1F0
BSY_
DONE
TF_RD_
DONE
CMD_
INTRQ_OK
reserved
Reset
-
0000
-
Bus reset
-
0000
-
Access
-
R/W
-
Table 73.
DMA Interrupt Reason register: bit description
Bit
Symbol
Description
15
TEST3
This bit is set when a DMA transfer for a packet (OUT transfer)
terminates before the whole packet is transferred. This bit is a
status bit, and the corresponding mask bit of this register is always
0. Writing any value other than 0 has no effect.
14 to 13
-
reserved
12
GDMA_STOP
GDMA Stop: When the GDMA_STOP command is issued to DMA
Command registers, it means the DMA transfer has successfully
terminated.
11
EXT_EOT
External EOT: Logic 1 indicates that an external EOT is detected.
This is applicable only in GDMA slave mode.
10
INT_EOT
Internal EOT: Logic 1 indicates that an internal EOT is detected;
9
INTRQ_
PENDING
Interrupt Pending: Logic 1 indicates that a pending interrupt was
detected on pin INTRQ.
8
DMA_XFER_OK
DMA Transfer OK: Logic 1 indicates that the DMA transfer is
completed (DMA Transfer Counter has become zero). This bit is
only used in GDMA (slave) mode and MDMA (master) mode.
7 to 5
-
reserved
4
READ_1F0
Read 1F0: Logic 1 indicates that the 1F0 FIFO contains unread
data and the microcontroller can start reading data.
3
BSY_DONE
Busy Done: Logic 1 indicates that the BSY status bit has become
zero and polling has been stopped.
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