參數(shù)資料
型號(hào)： ISP1583BS,551
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝： 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁(yè)數(shù)： 49/100頁(yè)
文件大?。?/td> 508K
代理商： ISP1583BS,551
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
51 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
[1]
The DREQ pin will be driven only after performing a write access to the DMA Conguration register (that is,
after conguring the DMA Conguration register).
Bit
7
6
5
4
3
2
1
0
Symbol
DIS_
XFER_CNT
reserved
MODE[1:0]
reserved
WIDTH
Reset
0
---
0
-
1
Bus reset
0
---
0
-
1
Access
R/W
-
R/W
-
R/W
Table 57.
DMA Conguration register: bit description
Bit
Symbol
15 to 14
-
reserved
13
ATA_MODE
ATA Mode: Mode selection of the DMA core.
0 — Congures the DMA core for non-ATA mode. Used when issuing
DMA commands 00h and 01h.
1 — Congures the DMA core for ATA or MDMA mode. Used when
issuing DMA commands 02h to 07h, 0Ah and 0Ch; also used when
directly accessing Task File registers.
12 to 11
DMA_MODE
[1:0]
DMA Mode: These bits affect the timing for MDMA mode.
00 — MDMA mode 0: ATA(PI) compatible timing
01 — MDMA mode 1: ATA(PI) compatible timing
10 — MDMA mode 2: ATA(PI) compatible timing
11 — MDMA mode 3: enables the DMA Strobe Timing register (see
Table 78 and Table 79) for non-standard strobe durations; only used in
MDMA mode
10 to 8
PIO_MODE
[2:0][2]
PIO Mode: These bits affect the PIO timing.
000 to 100 — PIO mode 0 to 4: ATA(PI) compatible timing
101 to 111 — reserved
7
DIS_XFER_
CNT
Disable Transfer Count: Logic 1 disables the DMA Transfer Counter
(see Table 54). The transfer counter can be disabled only in GDMA
slave mode; in master mode the counter is always enabled.
6 to 4
-
reserved
3 to 2
MODE[1:0]
Mode: These bits only affect GDMA (slave) and MDMA (master)
handshake signals.
00 — DIOR (master) or DIOW (slave): strobes data from the DMA bus
into the ISP1583; DIOW (master) or DIOR (slave): puts data from the
ISP1583 on the DMA bus.
01 — DIOR (master) or DACK (slave): strobes data from the DMA bus
into the ISP1583; DACK (master) or DIOR (slave): puts data from the
ISP1583 on the DMA bus.
10 — DACK (master and slave): strobes data from the DMA bus into
the ISP1583 and also puts data from the ISP1583 on the DMA bus.
11 — reserved
1
-
reserved
0
WIDTH
Width: This bit selects the DMA bus width for GDMA (slave) and
MDMA (master).
0 — 8-bit data bus
1 — 16-bit data bus
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ISP1583ET 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB peripheral controller
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