參數(shù)資料
型號: ISP1583BS,551
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁數(shù): 17/100頁
文件大小: 508K
代理商: ISP1583BS,551
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
22 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
8.15 Power-on reset
The ISP1583 requires a minimum pulse width of 500
s.
The RESET_N pin can either be connected to VCC(3V3) (using the internal POR circuit) or
externally controlled (by the microcontroller, ASIC, and so on). When VCC(3V3) is directly
connected to the RESET_N pin, internal pulse width tPORP will typically be 200 ns.
The power-on reset function can be explained by viewing the dips at t2 to t3 and t4 to t5
on the VCC(POR) curve (Figure 10).
t0 — The internal POR starts with a HIGH level.
t1 — The detector will see the passing of the trip level and a delay element will add
another tPORP before it drops to LOW.
t2 to t3 — The internal POR pulse will be generated whenever VCC(POR) drops below Vtrip
for more than 11
s.
t4 to t5 — The dip is too short (< 11
s) and the internal POR pulse will not react and will
remain LOW.
Figure 11 shows the availability of the clock with respect to the external POR.
(1) PORP = Power-On Reset Pulse.
Fig 10. POR timing
Power on VCC(3V3) at A.
Stable external clock is to be available at B.
The ISP1583 is operational at C.
Fig 11. Clock with respect to the external POR
004aab162
VCC(POR)
t0
t1
t2
t3
t4
t5
Vtrip
tPORP
PORP(1)
tPORP
VCC(3V3)
external
clock
A
004aaa906
500
s
RESET_N
2 ms
C
B
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