參數(shù)資料
型號(hào)： ISP1583BS,551
廠商： ST-ERICSSON
元件分類(lèi)： 總線(xiàn)控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝： 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁(yè)數(shù)： 39/100頁(yè)
文件大小： 508K
代理商： ISP1583BS,551
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
42 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Example 1: Consider that the transfer size is 512 bytes and the MaxPacketSize is
programmed as 64 bytes, the Buffer Length register need not be lled. This is because the
transfer size is a multiple of MaxPacketSize, and MaxPacketSize packets will be
automatically validated because the last packet is also of MaxPacketSize.
Example 2: Consider that the transfer size is 510 bytes and the MaxPacketSize is
programmed as 64 bytes, the Buffer Length register must be lled with 62 bytes just
before the microprocessor writes the last packet of 62 bytes. This ensures that the last
packet, which is a short packet of 62 bytes, is automatically validated.
Use bit VENDP in the Control register if you are not using the Buffer Length register.
This is applicable only to PIO mode access.
OUT endpoint: The DATACOUNT value is automatically initialized to the number of data
bytes sent by the host on each ACK.
Remark: When using a 16-bit microprocessor bus, the last byte of an odd-sized packet is
output as the lower byte (LSByte).
Remark: Buffer Length is valid only after an interrupt is generated for the OUT endpoint.
9.3.5 Buffer Status register (address: 1Eh)
This register is accessed using index. The endpoint index must rst be set before
accessing this register for the corresponding endpoint. It reects the status of the double
buffered endpoint FIFO.
Remark: This register is not applicable to the control endpoint.
Remark: For endpoint IN data transfer, rmware must ensure a 200 ns delay between
writing of the data packet and reading the Buffer Status register. For endpoint OUT data
transfer, rmware must also ensure a 200 ns delay between receiving the endpoint
interrupt and reading the Buffer Status register. For more information, refer to Ref. 3
Table 41.
Buffer Length register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
DATACOUNT[15:8]
Reset
00000000
Bus reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
DATACOUNT[7:0]
Reset
00000000
Bus reset
00000000
Access
R/W
Table 42.
Buffer Length register: bit description
Bit
Symbol
Description
15 to 0
DATACOUNT[15:0]
Data Count: Determines the current packet size of the indexed
endpoint FIFO.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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ISP1583BS-T 功能描述:USB 接口集成電路 USB PERIPH CNTRLR RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類(lèi)型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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ISP1583ET 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Hi-Speed USB peripheral controller
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