參數(shù)資料
型號: ISP1301
廠商: NXP Semiconductors N.V.
英文描述: Universal Serial Bus On-The-Go transceiver
中文描述: 通用串行總線在- The - Go的收發(fā)器
文件頁數(shù): 20/46頁
文件大?。?/td> 245K
代理商: ISP1301
Philips Semiconductors
ISP1301
USB OTG transceiver
Product data
Rev. 01 — 14 April 2004
20 of 46
9397 750 11355
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
OTG Status register (Read: 10H):
Table 23
shows the bit allocation of the OTG
Status register.
11.1.4
Interrupt related registers
Interrupt Source register (Read: 08H):
This register indicates the current state of
the signals that can generate an interrupt. The bit allocation of the Interrupt Source
register is given in
Table 25
.
Table 22:
Bit
7
6
5
4
3
2
1
0
OTG Control register: bit description
Symbol
Description
VBUS_CHRG
charge V
BUS
through a resistor to 3.3 V
VBUS_DISCHRG
discharge V
BUS
through a resistor to ground
VBUS_DRV
drive V
BUS
to 5 V through the charge pump
ID_PULLDOWN
connect the ID pin to ground
DM_PULLDOWN
connect DM pull-down resistor to ground
DP_PULLDOWN
connect DP pull-down resistor to ground
DM_PULLUP
connect DM pull-up resistor to 3.3 V
DP_PULLUP
connect DP pull-up resistor to 3.3 V
Table 23:
Bit
Symbol
OTG Status register: bit allocation
7
B_SESS_
VLD
0
R
6
5
4
3
2
1
0
B_SESS_
END
0
R
reserved
Reset
Access
0
R
0
R
0
R
0
R
0
R
0
R
Table 24:
Bit
7
OTG Status register: bit description
Symbol
Description
B_SESS_VLD
set when the V
BUS
voltage is above the B-device session valid
threshold (2.0 V to 4.0 V)
B_SESS_END
set when the V
BUS
voltage is below the B-device session end
threshold (0.2 V to 0.8 V)
-
reserved
6
5 to 0
Table 25:
Bit
Symbol
Interrupt Source register: bit allocation
7
CR_INT
BDIS_
ACON
0
R
6
5
4
3
2
1
0
ID_FLOAT
DM_HI
ID_GND
DP_HI
SESS_VLD
VBUS_VLD
Reset
Access
0
R
0
R
0
R
0
R
0
R
0
R
0
R
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