參數(shù)資料
型號(hào)： ISP1301
廠商： NXP Semiconductors N.V.
英文描述： Universal Serial Bus On-The-Go transceiver
中文描述： 通用串行總線在- The - Go的收發(fā)器
文件頁數(shù)： 13/46頁
文件大?。?/td> 245K
代理商： ISP1301
Philips Semiconductors
ISP1301
USB OTG transceiver
Product data
Rev. 01 — 14 April 2004
13 of 46
9397 750 11355
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table 6
specifies the functionality of the device during the four USB modes.
The ISP1301 is in the USB mode when both the TRANSP_EN and UART_EN bits
are cleared.
9.4 Transparent modes
9.4.1
Transparent general-purpose buffer mode
In the transparent general-purpose buffer mode, the DAT/VP and SE0/VM pins are
connected to the DP and DM pins, respectively. Using bits TRANSP_BDIR1 and
TRANSP_BDIR0 of the Mode Control 2 register as specified in
Table 8
, you can
control the direction of data transfer. The ISP1301 is in the transparent
general-purpose buffer mode if bit TRANSP_EN = 1 and bit DAT_SE0 = 1.
9.4.2
Transparent UART mode
When in the transparent UART mode, the ATX behaves as two logic level translator
between the following pins:
For TxD signal: from SE0/VM (V
DD_LGC
level) to DM (+3.3 V level)
For RxD signal: from DP (+3.3 V level) to DAT/VP (V
DD_LGC
level).
In the UART mode, the OTG controller is allowed to connect a UART to the DAT/VP
and SE0/VM pins of the ISP1301.
The UART mode is entered by setting the UART_EN bit in the Mode Control 1
register. The UART mode is equivalent to one of the transparent general purpose
buffer mode (bit TRANSP_BDIR1 = 1, bit TRANSP_BDIR0 = 0).
9.4.3
Summary tables
[1]
Conditions:
a) bit SPD_SUSP_CTRL
=
0 and pin SUSPEND
=
HIGH, or
b) bit SPD_SUSP_CTRL
=
1 and bit SUSPEND_REG
=
0.
Table 4:
Mode
Device operating modes
USB
suspend
condition
[1]
Bit
DAT
_SE0
Pin
OE_N/
INT_N
Bit
TRANSP
_EN
Bit
UART
_ EN
Description
Direct I
2
C-bus mode
Direct I
2
C-bus mode
X
X
X
X
X
1
X
HIGH
X
0
1
1
X
X
X
USB modes
USB suspend mode
USB functional mode
Transparent modes
Transparent general-purpose
buffer mode
Transparent UART mode
1
0
X
X
X
X
0
0
0
0
see
Table 5
and
Table 7
ATX is fully functional; see
Table 6
X
1
X
1
0
ATX is not functional; see
Table 8
X
X
X
X
1
DAT/VP <= DP (RxD signal of UART)
SE0/VM => DM (TxD signal of UART);
ATX is not functional
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