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參數(shù)資料
| 型號： | ISP1161 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Full-speed Universal Serial Bus single-chip host and device controller |
| 中文描述： | 全速通用串行總線的單芯片主機和設(shè)備控制器 |
| 文件頁數(shù)： | 86/127頁 |
| 文件大?。?/td> | 2762K |
| 代理商： | ISP1161 |
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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
86 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
The HCD must take care of the difference that the internal buffer RAM is organized in
bytes. The HCD must write the byte count into the HcTransferCounter register, but the
HCD reads or writes the buffer RAM by 16 bits (by 1 word).
13.6.7
HcATLBufferPort Register
This is the ATL buffer RAM read/write port. The bits 15:8 contain the data byte that
comes from the Acknowledged Transfer List (ATL) buffer RAM’s even address. The
bits 7:0 contain the data byte that comes from the ATL buffer RAM’s odd address.
Code (Hex): 41 —
read
Code (Hex): C1 —
write
The HCD must set the byte count into the HcTransferCounter register and check the
HcBufferStatus register before reading from or writing to the buffer. The HCD must
write the command (41H for read, C1H for write) once only, and then read or write all
the data bytes in word. After every read/write, the pointer of ATL buffer RAM will be
automatically increased by two to point to the next data word until it reaches the value
of HcTransferCounter register; otherwise, an internal EOT signal is not generated to
set the bit 2 AllEOTInterrupt, of the Hc
μ
PInterrupt register and update the
HcBufferStatus register.
The HCD must take care of the difference: the internal buffer RAM is organized in
bytes, so the HCD must write the byte count into the HcTransferCounter register, but
the HCD reads or writes the buffer RAM by 16 bits (by 1 word).
14. DC commands and registers
The functions and registers of ISP1161 are accessed via commands, which consist
of a command code followed by optional data bytes (read or write action). An
overview of the available commands and registers is given in
Table 74
.
A complete access consists of two phases:
Table 72: HcATLBufferPort Register: bit allocation
Bit
15
Symbol
Reset
0
Access
Bit
7
Symbol
Reset
0
Access
14
13
12
DataWord[15:8]
0
R/W
4
DataWord[7:0]
0
R/W
11
10
9
8
0
0
0
0
0
0
6
5
3
2
1
0
0
0
0
0
0
0
Table 73: HcATLBufferPort Register: bit description
Bit
Symbol
15 to 0
DataWord[15:0]
Description
Read/Write ATL buffer RAM’s two data bytes.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISP1161A1 | Universal Serial Bus single-chip host and device controller |
| ISP1161A1BD | Universal Serial Bus single-chip host and device controller |
| ISP1161A1BM | Universal Serial Bus single-chip host and device controller |
| ISP1161BD | Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1161BM | Full-speed Universal Serial Bus single-chip host and device controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1161A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1161A1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Serial Bus single-chip host and device controller |
| ISP1161A1BD | 功能描述:IC USB HOST/DEVICE CTRLR 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1161A1BD,118 | 功能描述:USB 接口集成電路 USB1.1 HOST &DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1161A1BD,151 | 功能描述:USB 接口集成電路 USB1.1 HOST &DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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