參數(shù)資料
型號: ISP1161
廠商: NXP Semiconductors N.V.
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: 全速通用串行總線的單芯片主機和設備控制器
文件頁數(shù): 76/127頁
文件大?。?/td> 2762K
代理商: ISP1161
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
76 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
13.4 HC DMA and interrupt control registers
13.4.1
HcHardwareConfiguration Register
Table 44: HcHardwareConfiguration Register: bit allocation
Bit
15
Symbol
reserved
14
13
12
11
10
9
8
2_Down
streamPort
15K
resistorsel
0
R/W
4
DataBusWidth
Suspend
ClkNotStop
AnalogOC
Enable
reserved
DACKMode
Reset
Access
Bit
Symbol
0
0
0
0
0
0
0
R/W
6
R/W
3
R/W
2
R/W
1
R/W
0
7
5
EOTInput
Polarity
0
R/W
DACKInput
Polarity
0
R/W
DREQOut
putPolarity
0
R/W
InterruptOut
putPolarity
0
R/W
InterruptPi
nTrigger
0
R/W
InterruptPin
Enable
0
R/W
Reset
Access
0
1
R/W
Table 45: HcHardwareConfiguration Register: bit description
Bit
Symbol
15 to 13
-
12
2_DownstreamPort15KresistorSel
Description
reserved
0 —
use external 15 k
resistors for downstream ports
1 —
use built-in resistors for downstream ports
0 —
Clk can be stopped
1 —
clock can not be stopped
0 —
use external OC detection. Digital input
1 —
use on-chip OC detection. Analog input
reserved
0 —
normal operation. DACK1 is used with read and write signals.
Power-up value.
1 —
reserved
0 —
active LOW. Power-up value
1 —
active HIGH
0 —
active LOW. Power-up value
1 —
active HIGH
0 —
active LOW
1 —
active HIGH. Power-up value
01 —
16 bits
Others —
reserved
0 —
active LOW. Power-up value
1 —
active HIGH
0 —
interrupt is level-triggered. Power-up value
1 —
Interrupt is edge-triggered.
0 —
power-up value
1 —
pin Global Interrupt INT1 is enabled
11
SuspendClkNotStop
10
AnalogOCEnable
9
8
-
DACKMode
7
EOTInputPolarity
6
DACKInputPolarity
5
DREQOutputPolarity
4 to 3
DataBusWidth[1:0]
2
InterruptOutputPolarity
1
InterruptPinTrigger
0
InterruptPinEnable
相關PDF資料
PDF描述
ISP1161A1 Universal Serial Bus single-chip host and device controller
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