參數(shù)資料
型號: ISP1160BD/01,118
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 63/88頁
文件大?。?/td> 394K
代理商: ISP1160BD/01,118
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 05 — 24 December 2004
66 of 88
9397 750 13963
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10.6.5
HcReadBackITL1Length register (R: 2EH)
This register’s value stands for the current number of data bytes inside the ITL1 buffer
to be read back by the microprocessor. The HCD must set the HcTransferCounter
equivalent to this value before reading back the ITL1 buffer RAM.
Code (Hex): 2E — read
10.6.6
HcITLBufferPort register (R/W: 40H/C0H)
This is the ITL buffer RAM read/write port. The bits 15:8 contain the data byte that
comes from the ITL buffer RAM’s even address. The bits 7:0 contain the data byte
that comes from the ITL buffer RAM’s odd address.
Code (Hex): 40 — read
Code (Hex): C0 — write
Table 58:
HcReadBackITL0Length register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
RdITL0BufferLength[15:8]
Reset
00000000
Access
RRRRRRRR
Bit
7
6
5
4
3
2
1
0
Symbol
RdITL0BufferLength[7:0]
Reset
00000000
Access
RRRRRRRR
Table 59:
HcReadBackITL0Length register: bit description
Bit
Symbol
Description
15 to 0
RdITL0BufferLength[15:0]
The number of bytes for ITL0 data to be read back by
the microprocessor
Table 60:
HcReadBackITL1Length register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
RdITL1BufferLength[15:8]
Reset
00000000
Access
RRRRRRRR
Bit
7
6
5
4
3
2
1
0
Symbol
RdITL1BufferLength[7:0]
Reset
00000000
Access
RRRRRRRR
Table 61:
HcReadBackITL1Length register: bit description
Bit
Symbol
Description
15 to 0
RdITL1BufferLength[15:0]
The number of bytes for ITL1 data to be read back by
the microprocessor.
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