參數(shù)資料
型號: ISP1160BD/01,118
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 2/88頁
文件大?。?/td> 394K
代理商: ISP1160BD/01,118
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 05 — 24 December 2004
10 of 88
9397 750 13963
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.3 Control registers access by PIO mode
8.3.1
I/O port addressing
Table 3 shows the ISP1160’s I/O port addressing. Complete decoding of the I/O port
address should include the chip select signal CS_N and the address line A0.
However, the direction of access of I/O ports is controlled by the RD_N and
WR_N signals. When RD_N is LOW, the microprocessor reads data from the
ISP1160’s data port. When WR_N is LOW, the microprocessor writes a command to
the command port, or writes data to the data port.
Figure 5 illustrates how an external microprocessor accesses the ISP1160’s internal
control registers.
8.3.2
Register access phases
The ISP1160’s register structure is a command-data register pair structure. A
complete register access cycle comprises a command phase followed by a data
phase. The command (also known as the index of a register) points the ISP1160 to
the next register to be accessed. A command is 8 bits long. On a microprocessor’s
16-bit data bus, a command occupies the lower byte, with the upper byte lled with
zeros.
Figure 6 shows a complete 16-bit register access cycle for the ISP1160. The
microprocessor writes a command code to the command port, and then reads from or
writes the data word to the data port. Take the example of a microprocessor
attempting to read the ISP1160’s ID, which is saved in the HC’s HcChipID register
(index 27H, read only). The 16-bit register access cycle is therefore:
1. The microprocessor writes the command code of 27H (0027H in 16-bit width) to
the HC command port
2. The microprocessor reads the data word of the chip’s ID from the HC data port.
Table 3:
I/O port addressing
Port
CS_N
A0
Access
Data bus width
(bits)
Description
0
R/W
16
HC data port
101W
16
HC command port
When A0
= 0, microprocessor accesses the data port.
When A0
= 1, microprocessor accesses the command port.
Fig 5.
Access to internal control registers.
004aaa075
CMD/DATA
SWITCH
Commands
Control registers
Command register
data port
A0
command port
..
.
Host bus I/F
1
0
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