參數(shù)資料
型號(hào): ISP1160BD/01,118
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù): 10/88頁(yè)
文件大小: 394K
代理商: ISP1160BD/01,118
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 05 — 24 December 2004
18 of 88
9397 750 13963
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Description of Figure 15:
1. Reset
This includes hardware reset by pin RESET_N and software reset by the
HcSoftwareReset command (A9H). The reset function will clear all the HC’s
internal control registers to their reset status. After reset, the HCD must initialize
the ISP1160 USB HC by setting some registers.
2. Initialize HC
It includes:
a. Setting the physical size for the HC’s internal FIFO buffer RAM by setting the
HcITLBufferLength register (2AH to read, AAH to write) and the
HcATLBufferLength register (2BH to read, ABH to write).
b. Setting the HcHardwareConguration register according to requirements.
c. Clearing interrupt events, if required.
d. Enabling interrupt events, if required.
e. Setting the HcFmInterval register (0DH to read, 8DH to write).
f. Setting the HC’s Root Hub registers.
g. Setting the HcControl register to move the HC into the USBOperational state.
See also Section 9.5.
3. Entry
The normal entry point. The microprocessor returns to this point when there are
HC requests.
4. Need USB trafc
USB devices need the HC to generate USB trafc when they have USB trafc
requests such as:
a. Connecting to or disconnecting from downstream ports
b. Issuing the Resume signal to the HC.
To generate USB trafc, the HCD must enter the USB transaction loop.
Fig 15. ISP1160 HC USB transaction loop.
MGT948
Need
USB traffic?
Prepare PTD data in
P system RAM
Initialize
HC
Transfer PTD data into
HC FIFO buffer RAM
HC performs USB transactions
via USB bus I/F
HC informs HCD of
USB traffic results
HC interprets
PTD data
Exit
Entry
HC state =
USBOperational
no
yes
Reset
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