參數(shù)資料
型號(hào): ISP1160BD/01,118
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù): 43/88頁(yè)
文件大小: 394K
代理商: ISP1160BD/01,118
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 05 — 24 December 2004
48 of 88
9397 750 13963
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10.3 HC Root Hub registers
All registers included in this partition are dedicated to the USB Root Hub, which is an
integral part of the HC although it is functionally a separate entity. The Host Controller
Driver (HCD) emulates USBD accesses to the Root Hub via a register interface. The
HCD maintains many USB-dened hub features that are not required to be supported
in hardware. For example, the Hub’s Device, Conguration, Interface, and Endpoint
Descriptors, as well as some static elds of the Class Descriptor, are maintained only
in the HCD. The HCD also maintains and decodes the Root Hub’s device address as
well as other minor operations more suited for software than hardware.
The Root Hub registers were developed to match the bit organization and operation
of typical hubs found in the system.
Four 32-bit registers have been dened:
HcRhDescriptorA
HcRhDescriptorB
HcRhStatus
HcRhPortStatus[1:NDP]
Each register is read and written as a DWORD. These registers are only written
during initialization to correspond with the system implementation. The
HcRhDescriptorA and HcRhDescriptorB registers are writeable regardless of the
HC’s USB states. HcRhStatus and HcRhPortStatus are writeable during the
USBOperational state only.
10.3.1
HcRhDescriptorA register (R/W: 12H/92H)
The HcRhDescriptorA register is the rst register of two describing the characteristics
of the Root Hub. Reset values are implementation-specic (IS). The descriptor length
(11), descriptor type and hub controller current (0) elds of the hub Class Descriptor
are emulated by the HCD. All other elds are located in registers HcRhDescriptorA
and HcRhDescriptorB.
Remark: IS denotes an implementation-specic reset value for that eld.
Code (Hex): 12 — read
Code (Hex): 92 — write
Table 27:
HcLSThreshold register: bit description
Bit
Symbol
Description
31 to 11
reserved
10 to 0
LST[10:0]
LSThreshold: Contains a value that is compared to the
FrameRemaining eld before a low-speed transaction is initiated.
The transaction is started only if FrameRemaining
≥ this eld. The
value is calculated by the HCD, which considers transmission and
set-up overhead.
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