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| 型號： | ISL12022MAIBZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 15/31頁 |
| 文件大小： | 0K |
| 描述： | IC RTC/CALENDAR TEMP SNSR 20SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 38 |
| 類型： | 時鐘/日歷 |
| 特點(diǎn)： | 警報器，夏令時，閏年，SRAM |
| 存儲容量： | 128B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC |
| 包裝： | 管件 |
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ISL12022MA
22
FN7575.5
September 5, 2012
To clear a single event alarm, the ALM bit in the status register
must be set to “0” with a write. Note that if the ARST bit is set to
1 (address 08h, Bit 7), the ALM bit will automatically be cleared
when the status register is read.
Following are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1
Alarm set with single interrupt (IM = “0”)
A single alarm will occur on January 1 at 11:30 a.m.
Set Alarm registers as follows:
After these registers are set, an alarm will be generated when the
RTC advances to exactly 11:30 a.m. on January 1 (after seconds
changes from 59 to 00) by setting the ALM bit in the status register
to “1” and also bringing the IRQ/FOUT output low.
Example 2
Pulsed interrupt once per minute (IM = “1”)
Interrupts at one minute intervals when the seconds register is
at 30 seconds.
Set Alarm registers as follows:
Once the registers are set, the following waveform will be seen at
IRQ/FOUT:
Note that the status register ALM bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
Time Stamp VDD to Battery Registers (TSV2B)
The TSV2B Register bytes are identical to the RTC register bytes,
except they do not extend beyond the Month. The Time Stamp
captures the FIRST VDD to Battery Voltage transition time, and will
not update upon subsequent events until cleared (only the first event
is captured before clearing). Set CLRTS = 1 to clear this register (Add
09h, PWR_VDD register).
Note that the time stamp registers are cleared to all “0”,
including the month and day, which is different from the RTC and
alarm registers (those registers default to 01h). This is the
indicator that no time stamping has occurred since the last clear
or initial power-up. Once a time stamp occurs, there will be a non-
zero time stamp.
Time Stamp Battery to VDD Registers (TSB2V)
The Time Stamp Battery to VDD Register bytes are identical to
the RTC register bytes, except they do not extend beyond Month.
The Time Stamp captures the LAST transition of VBAT to VDD
(only the last event of a series of power-up/power-down events is
retained). Set CLRTS = 1 to clear this register (Add 09h, PWR_VDD
register).
ALARM
REGISTER
BIT
DESCRIPTION
76 543 21 0
HEX
SCA0
00 00 000 0
00h Seconds disabled
MNA0
10 11 000 0
B0h Minutes set to 30,
enabled
HRA0
10 01 000 1
91h Hours set to 11,
enabled
DTA0
10 00 000 1
81h Date set to 1,
enabled
MOA0
10 00 000 1
81h Month set to 1,
enabled
DWA0
00 00 000 0
00h Day of week
disabled
TABLE 21.
ALARM
REGISTER
BIT
DESCRIPTION
76543 210 HEX
SCA0
10110 000 B0h Seconds set to 30,
enabled
MNA0
00000 000 00h Minutes disabled
HRA0
00000 000 00h Hours disabled
DTA0
00000 000 00h Date disabled
MOA0
00000 000 00h Month disabled
DWA0
00000 000 00h Day of week disabled
60s
RTC AND ALARM REGISTERS ARE BOTH “30s”
FIGURE 15. IRQ/FOUT WAVEFORM
TABLE 22. DST FORWARD REGISTERS
ADDRESS
FUNCTION
7
6
54321
0
20h
Month Forward
DSTE
0
MoFd20
MoFd13
MoFd12
MoFd11
MoFd10
21h
Day Forward
0
DwFdE
WkFd12
WkFd11
WkFd10
DwFd12
DwFd11
DwFd10
22h
Date Forward
0
DtFd21
DtFd20
DtFd13
DtFd12
DtFd11
DtFd10
23h
Hour Forward
0
HrFd21
HrFd20
HrFd13
HrFd12
HrFd11
HrFd10
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