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參數(shù)資料
| 型號(hào)： | IRGB430 |
| 廠商： | International Rectifier |
| 英文描述： | INSULATED GATE BIPOLAR TRANSISTOR(Vces=500V, @Vge=15V, Ic=15A) |
| 中文描述： | 絕緣柵雙極晶體管（VCES和\u003d的500V，@和VGE \u003d 15V的，集成電路\u003d 15A條） |
| 文件頁數(shù)： | 8/8頁 |
| 文件大?。?/td> | 425K |
| 代理商： | IRGB430 |
C-632
IRGB430UD2
t1
Ic
Vce
t1
t2
90% Ic
10% Vce
td(off)
tf
Ic
5% Ic
t1+5μS
Vce ic dt
∫
90% Vge
+Vge
Eoff =
Fig. 18b
-
Test Waveforms for Circuit of Fig. 18a, Defining
E
off
, t
d(off)
, t
f
Same type
D.U.T.
430μF
80%
Fig. 18a
-
Test Circuit for Measurement of
I
LM
, E
on
, E
off(diode)
, t
rr
, Q
rr
, I
rr
, t
d(on)
, t
r
, t
d(off)
, t
f
∫
t1
Vce ie dt
t2
5% Vce
Ic
Ipk
Vcc
10% Ic
Vce
t1
t2
DUT VOLTAGE
AND CURRENT
GATE VOLTAGE D.U.T.
+Vg
10% +Vg
90% Ic
tr
td(on)
DIODE REVERSE
RECOVERY ENERGY
tx
10% Vcc
Eon =
∫
t3
Erec =
t4
Vd id dt
t4
t3
DIODE RECOVERY
WAVEFORMS
Ic
Vpk
Irr
10% Irr
Vcc
trr
∫
tx
Qrr =
trr
id dt
Fig. 18c
-
Test Waveforms for Circuit of Fig. 18a,
Defining E
on
, t
d(on)
, t
r
Refer to Section D for the following:
Fig. 18d
-
Test Waveforms for Circuit of Fig. 18a,
Defining E
rec
, t
rr
, Q
rr
, I
rr
Appendix B: Section D - page D-4
Fig. 18e - Macro Waveforms for Test Circuit Fig. 18a
Fig. 19 - Clamped Inductive Load Test Circuit
Fig. 20 - Pulsed Collector Current Test Circuit
Package Outline 1
- JEDEC Outline TO-220AB
Section D - page D-12
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