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參數(shù)資料
| 型號： | IR3Y48A1 |
| 廠商： | Sharp Corporation |
| 英文描述： | CCD SIGNAL PROCESS & DIGITAL INTERFACE IC |
| 中文描述： | 防治荒漠化公約信號處理 |
| 文件頁數(shù)： | 8/31頁 |
| 文件大?。?/td> | 176K |
| 代理商： | IR3Y48A1 |
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8
IR3Y48M
Clamp Circuit
DC CLAMP
DC level of the analog input is fixed by internal DC
clamp circuit. DC level of C-coupled CCD signal at
CDS input is set to CLPCAP by DC clamping.
Normally clamp switch is turned on at black level
calibration
period.
Place
capacitance between CLPCAP and AV
SS
.
0.1
μF
external
(Register Conditions)
REFIN
CCDIN
SHR
SHD CCDCLP
Clamp
Source
CLPCAP
DC Clamp Function
(CCDCLP)
CLPCAP
CCDCLP
ADCK
CCD
CLPCAP Level
REFIN, CCDIN
Clamp Level
Clamp Timing
CLAMP OF ADIN SIGNAL
Clamp operation for ADIN path is also available.
Note that clamp voltage [CLPCAP] is different
between CCD input and ADIN.
ADCLP signal is used for both clamp and black
level control at ADIN input mode. It is also possible
to turn off clamp operation by register setting.
CLAMP CONTROL
Following items are selectable through register
setting.
a) Clamp current
Normal or fast clamp is selectable for charge
current. (Select normal clamp in general)
b) Clamp target
Input signal (REFIN and CCDIN) to be
clamped is selectable. It is also possible to turn
off the clamp function.
ADCLP
ADIN
To AGC
or
To ADC
Timing Control
CLPCAP
(ADCLP)
ADIN DC Clamp Function
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