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參數(shù)資料
| 型號(hào)： | IR3Y48A1 |
| 廠商： | Sharp Corporation |
| 英文描述： | CCD SIGNAL PROCESS & DIGITAL INTERFACE IC |
| 中文描述： | 防治荒漠化公約信號(hào)處理 |
| 文件頁數(shù)： | 12/31頁 |
| 文件大小： | 176K |
| 代理商： | IR3Y48A1 |
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12
IR3Y48M
Other Functions
ADC DIRECT INPUT (ADIN MODE)
Direct input path to ADC or AGC is realized by
register setting. This direct path can be turned off
by register. Black level cancel and clamp are
performed at the same timing of ADCLP low.
These controls can be masked by register setting.
BLK, SHR, and SHD controls are ignored at ADIN
mode.
The signal at AGC input is shown below.
Operation at ADC direct input is shown below.
The zero reference (CLPCAP) is established by
ADCLP pulse. The ADIN input range is from
CLPCAP + 1 V (TYP.) (full scale).
ADIN
(N)
N – 8 N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1
N
(N+1)
(N+2)
ADCK
(When ADCK is inverted,
signal (N) is sampled by this edge)
ADCLP
Black Cancel & Clamp
DO
0
-DO
9
ADIN Signal Processing (AGC Input)
NOTE :
For ADCLP low, both black level cancel and clamp are active at AGC input mode, and only clamp is active at
ADC input mode.
Clamp ON
Full scale
CLPCAP + 1 V
ADC
dynamic range
= 1 Vp-p
CLPCAP
ADIN
ADCLP
ADIN Signal Input Level
STANDBY MODE
The standby mode can be set either by register
setting or STBYN pin.
If one of the above is set, IR3Y48M powers down.
("OR" logic)
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