參數(shù)資料
型號: IR3Y48A1
廠商: Sharp Corporation
英文描述: CCD SIGNAL PROCESS & DIGITAL INTERFACE IC
中文描述: 防治荒漠化公約信號處理
文件頁數(shù): 10/31頁
文件大?。?/td> 176K
代理商: IR3Y48A1
10
IR3Y48M
Gain Control Circuit
The total gain for CCD input signal covers from 0 to
36 dB.
This range consists of CDS (0 to 12 dB (6 dB/
step)), AGC rough (0 to 18 dB (6 dB/step)), and
AGC fine (0 to 6 dB (0.094 dB/step)). Total gain is
controlled (as described below) by 9-bit gain control
register. The gain is fixed to maximum gain when
the code exceeds 382 (decimal).
The gain of ADIN (which bypassing CDS) is 0 to
24 dB.
0D
0 dB
35.91 dB
0.094 dB
1 step
383D
CDS
6 dB/step
(0 to 12 dB)
Rough
6 dB/step
(0 to 18 dB)
AGC Block
Fine
0.094 dB/step
(0 to 6 dB)
Total Gain = 0 to 35.91 dB
Gain Control
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