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參數(shù)資料
| 型號(hào)： | IR3Y48A1 |
| 廠商： | Sharp Corporation |
| 英文描述： | CCD SIGNAL PROCESS & DIGITAL INTERFACE IC |
| 中文描述： | 防治荒漠化公約信號(hào)處理 |
| 文件頁(yè)數(shù)： | 7/31頁(yè) |
| 文件大?。?/td> | 176K |
| 代理商： | IR3Y48A1 |
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7
IR3Y48M
Reference Clock (SHR)
Data Clock (SHD)
REFIN
CCDIN
CCD
CDS
CDS Output
= V (CDS)
= V (DAT) – V (PREC)
Reset
Pulse
Reset
Pulse
V (PREC)
V (DAT)
MAX. Level
SHR
SHR
SHD
SHD
SIG
f
SMAX
= 20 MHz
/
t
SMIN
= 50 ns
SIG
V (CDS)
CDS Operation
CDS Circuit
CDS circuit holds CCD precharge (reference) level
at SHR pulse, then it samples CCD pixel data at
SHD pulse. Correlated (common) noise is removed
by subtraction of precharge level from pixel data
level.
CDS has the gain of maximum 12 dB (6 dB/step).
This gain is a part of total gain and it is controlled
by register value similar to gain in AGC circuit.
Connect signal from CCD sensor to CCDIN pin
through C-coupling. Place the same capacitor
between REFIN and AV
SS
.
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