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參數(shù)資料
| 型號： | IDTCV109EPV |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | CMOS/TTL Compatible |
| 中文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 104K |
| 代理商： | IDTCV109EPV |
COMMERCIAL TEMPERATURE RANGE
6
IDTCV109E
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
ONECYCLE INDEX BLOCK READ
Bit
#of bits
From
1
1
Master
Start
2-9
8
Master
D2h
10
1
Slave
Acknowledge
11-18
8
Master
Register offset byte (starting byte)
19
1
Slave
Acknowledge
20-27
8
Master
1xxxxxxx. Bit[20] = 1, followed with byte
count, which will be stored into SMBus table
byte 8.
28
1
Slave
Acknowledge
29
1
Master
Repeated start
30-37
8
Master
D3h
38
1
Slave
Acknowledge
39-46
8
Slave
Byte count, N, SMBus table byte 8 value.
Power on default is 0FH[15].
47
1
Master
Acknowledge
48-55
8
Slave
Offset data byte, specified by bit[11:18]
56
1
Master
Acknowledge
57-64
8
Slave
Offset + 1 data byte
:
Slave
Offset + N-2
Master
Acknowledge
Slave
Offset + N-1
Not acknowledge
Stop
Description
BY TE READ METHODS (CHOSE ONE):
Use IDT OneCycle Index Block Read, bit[20:27] = 10000001.
Notice that byte count register (byte 8) will be changed to 0IH.
Use Index Block Write protocol to change byte count (byte 8) to
1. After that, use Index Block Read.
TO CHANGE BY TE 8 VALUE:
Use IDT OneCycle Index Block Read, as above
Use Index Block Write protocol to change byte 8 value.
SMBUS PROTOCOL
INDEX BLOCK READ PROTOCOL
Bit
#of bits
From
1
1
Master
2-9
8
Master
10
1
Slave
11-18
8
Master
19
1
Slave
20
1
Master
21-28
8
Master
29
1
Slave
30-37
8
Slave
Description
Start
D2h
Acknowledge
Register offset byte (starting byte)
Acknowledge
Repeated start
D3h
Acknowledge
Byte count, N, SMBus table byte 8 value.
Power on default is 0FH[15].
Acknowledge
Offset data byte, specified by bit 11-18
Acknowledge
Offset + 1 data byte
:
Offset + N-2
Acknowledge
Offset + N-1
Not acknowledge
Stop
38
1
8
1
8
Master
Slave
Master
Slave
39-46
47
48-55
Slave
Master
Slave
INDEX BLOCK WRITE PROTOCOL
Bit
#of bits
From
1
1
Master
Start
2-9
8
Master
D2h
10
1
Slave
Acknowledge
11-18
8
Master
Register offset byte (starting byte)
19
1
Slave
Acknowledge
20-27
8
Master
Byte count N (0 is not a valid byte count)
(1)
28
1
Slave
Acknowledge
29-36
8
Master
First data byte
37
1
Slave
Acknowledge
38-45
8
Master
Second data byte
46
1
Slave
Acknowledge
:
Nth data byte
Stop
Description
NOTE:
1. Bit [21:27] = byte count.
Bit 20 = 1, bit [21:27] will be stored into SMBus table, Byte 8. SMBus Byte 8 is read
byte count register, power on default is 0FH.
Bit 20 = 0, normal SMbus operation.
BY TE WRITE METHODS:
Setting bit[11:18] = starting address, bit [20:27] = 01H.
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| IDTCV119EPV | CLOCK GENERATOR FOR DESKTOP PC PLATFORMS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTCV110JP | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
| IDTCV110JPV | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
| IDTCV110JPVG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
| IDTCV110L | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
| IDTCV110LPV | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
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