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參數(shù)資料
| 型號： | IDTCV109EPV |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | CMOS/TTL Compatible |
| 中文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 104K |
| 代理商： | IDTCV109EPV |
COMMERCIAL TEMPERATURE RANGE
IDTCV109E
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
15
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
IH
3.3V Input HIGH Voltage
3.3V ± 5%
2
—
V
DD
+ 0.3
V
V
IL
I
IH
3.3V Input LOW Voltage
Input HIGH Current
3.3V ± 5%
V
IN
= V
DD
V
SS
- 0.3
–5
—
—
0.8
5
V
μA
I
IL1
Input LOW Current
V
IN
= 0V, inputs with no pull-up resistors
–5
—
—
μA
I
IL2
Input LOW Current
V
IN
= 0V, inputs with pull-up resistors
–200
—
—
μA
I
DD3.3OP
I
DD3.3PD
Operating Supply Current
Powerdown Current
Full active, C
L
= full load
All differential pairs driven
All differential pairs tri-stated
—
—
—
—
—
—
400
70
12
mA
mA
F
I
Input Frequency
(2)
Pin Inductance
(3)
V
DD
= 3.3V
—
14.31818
—
MHz
L
PIN
—
—
7
nH
C
IN
Logic inputs
—
—
5
C
OUT
Input Capacitance
(3)
Output pin capacitance
—
—
6
pF
C
INX
X1 and X2 pins
—
—
5
T
STAB
Clock Stabilization
(3,4)
Modulation Frequency
(3)
T
DRIVE
_SRC
(3)
T
DRIVE
_PD#
(3)
T
FALL
_PD#
(3)
T
RISE
_PD#
(4)
T
DRIVE
_CPU_Stop#
(3)
T
FALL
_CPU_Stop#
(3)
T
RISE
_CPU_Stop#
(4)
FromV
DD
power-up or de-assertion of PD#to first clock
—
—
1.8
ms
Triangular modulation
30
—
33
KHz
SRC output enable after PCI_Stop#de-assertion
—
—
15
ns
CPU output enable after PD#de-assertion
—
—
300
us
Fall time of PD#
—
—
5
ns
Rise time of PD#
—
—
5
ns
CPU output enable after CPU_Stop#de-assertion
—
—
10
us
Fall time of PD#
—
—
5
ns
Rise time of PD#
—
—
5
ns
ELECT RICAL CHARACT ERIS T ICS - INPUT / S UPPLY / COMMON OUT PUT
PARAMETERS
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= 0°C to +70°C, Supply Voltage: V
DD
= 3.3V ± 5%
NOTES:
1. Available to CV104, CV105, CV107, and CV109.
2. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppmfrequency accuracy on PLL outputs.
3. This parameter is guaranteed by design, but not 100% production tested.
4. See TIMING DIAGRAMS for timng requirements.
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相關(guān)代理商/技術(shù)參數(shù) |
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| IDTCV110JP | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
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| IDTCV110JPVG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
| IDTCV110L | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
| IDTCV110LPV | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
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