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參數(shù)資料
| 型號： | IDTCV109EPV |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | CMOS/TTL Compatible |
| 中文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 1/21頁 |
| 文件大?。?/td> | 104K |
| 代理商： | IDTCV109EPV |
COMMERCIAL TEMPERATURE RANGE
IDTCV109E
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
1
J ANUARY 2004
COMME RCIAL T E MPE RAT URE RANGE
XTAL
Osc Amp
SM Bus
Watch Dog
Timer
Control
Logic
CPU CLK
Output Buffers
O3V66/PCI
SRC CLK
Output Buffer
48MHz
Output Buffer
X1
X2
SDATA
SCLK
V
TT_PWRGD
FS[1:0]
S
EL
24_48#
I
REF
I
REF
CPU[1:0]
REF 1.0
PCI[7:0], PCIF[2:0]
SRC
48MHz[1:0]
24 - 48MHz
PLL3
SSC
PLL4
PLL1
SSC
EasyN
Programming
PLL2
SSC
EasyN
Programming
RESET#
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2004 Integrated Device Technology, Inc.
DSC-6391/14
FUNCTIONAL BLOCK DIAGRAM
OUTPUT TABLE
CPU (Pair)
2
3V66
3
3V66/VCH
1
PCI
8
PCIF
3
REF
2
48MHz
1
24 - 48MHz
1
SRC (Pair)
1
Reset#
1
IDTCV109E
CLOCK GENERATOR FOR
DESKTOP PC PLATFORMS
FEATURES:
4 PLL architecture
Linear frequency programming
Independent frequency programming and SSC control
Band-gap circuit for differential output
High power-noise rejection ratio
66MHz to 533MHz CPU frequency
VCO frequency up to 1.1G
Support index block read/write, single cycle index block read
Programmable REF, 3V66, PCI, 48MHz I/O drive strength
Programmable 3V66 and PCI Skew
Available in SSOP package
DESCRIPTION:
IDTCV109E is a 48 pin clock generation device for desktop PC platforms.
This chip incorporates four PLLs to allow independent generation of CPU, AGP/
PCI, SRC, and 48MHz clocks. The dedicated PLL for Serial ATA clock
provides high accuracy frequency. This device also implements Band-gap
referenced I
REF
to reduce the impact of V
DD
variation on differential outputs,
which can provide more robust systemperformance.
Static PLL frequency divide error can be as low as 36 ppm providing high
accuracy output clock. Each CPU, AGP/PCI, SRC clock has its own Spread
Spectrumselection.
K EY SPECIFICATION:
CPU/SRC CLK cycle to cycle jitter < 125ps
SATA CLK cycle to cycle jitter < 125ps
PCI CLK cycle to cycle jitter < 250ps
Static PLL frequency divide error as low as 36 ppm
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| IDTCV119EPV | CLOCK GENERATOR FOR DESKTOP PC PLATFORMS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTCV110JP | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
| IDTCV110JPV | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
| IDTCV110JPVG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
| IDTCV110L | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
| IDTCV110LPV | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
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