參數(shù)資料
型號: IDT82V3288
廠商: Integrated Device Technology, Inc.
英文描述: WAN PLL
中文描述: 廣域網(wǎng)鎖相環(huán)
文件頁數(shù): 33/170頁
文件大?。?/td> 1053K
代理商: IDT82V3288
IDT82V3288
WAN PLL
Functional Description
33
June 22, 2006
Figure 7. T0 Selected Input Clock vs. DPLL Automatic Operating Mode
Notes to
Figure 7
:
1. Reset.
2. An input clock is selected.
3. The T0 selected input clock is disqualified
AND
No qualified input clock is available.
4. The T0 selected input clock is switched to another one.
5. The T0 selected input clock is locked (the T0_DPLL_LOCK bit is ‘1’).
6. The T0 selected input clock is disqualified
AND
No qualified input clock is available.
7. The T0 selected input clock is unlocked (the T0_DPLL_LOCK bit is ‘0’).
8. The T0 selected input clock is locked again (the T0_DPLL_LOCK bit is ‘1’).
9. The T0 selected input clock is switched to another one.
10. The T0 selected input clock is locked (the T0_DPLL_LOCK bit is ‘1’).
11. The T0 selected input clock is disqualified
AND
No qualified input clock is available.
12. The T0 selected input clock is switched to another one.
13. The T0 selected input clock is disqualified
AND
No qualified input clock is available.
14. An input clock is selected.
15. The T0 selected input clock is switched to another one.
Free-Run mode
1
Pre-Locked
mode
2
3
4
Locked
mode
5
Lost-Phase
mode
Holdover
mode
7
8
Pre-Locked2
mode
13
14
15
6
12
11
9
10
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