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參數(shù)資料
| 型號(hào)： | IDT82V3288 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | WAN PLL |
| 中文描述： | 廣域網(wǎng)鎖相環(huán) |
| 文件頁數(shù)： | 22/170頁 |
| 文件大?。?/td> | 1053K |
| 代理商： | IDT82V3288 |
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IDT82V3288
WAN PLL
Functional Description
22
June 22, 2006
3.4
INPUT CLOCK PRE-DIVIDER
Each input clock is assigned an internal Pre-Divider. The Pre-Divider
is used to divide the clock frequency down to the DPLL required fre-
quency, which is no more than 38.88 MHz.
For IN1 and IN2, the DPLL required frequency is fixed to 8 kHz (i.e.,
the corresponding IN_FREQ[3:0] bits are ‘0000’). The 8 kHz clock is
extracted from the composite clock and the Pre-Divider is bypassed
automatically.
For IN3 ~ IN14, the DPLL required frequency is set by the corre-
sponding IN_FREQ[3:0] bits.
If the input clock is of 2 kHz, 4 kHz or 8 kHz, the Pre-Divider is
bypassed automatically and the corresponding IN_FREQ[3:0] bits
should be set to match the input frequency; the input clock can be
inverted, as determined by the IN_2K_4K_8K_INV bit.
Each Pre-Divider consists of a HF (High Frequency) Divider (only
available for IN5 and IN6), a DivN Divider and a Lock 8k Divider, as
shown in
Figure 3
.
The HF Divider, which is only available for IN5 and IN6, should be
used when the input clock is higher than (
>
) 155.52 MHz. The input
clock can be divided by 4, 5 or can bypass the HF Divider, as deter-
mined by the IN5_DIV[1:0]/IN6_DIV[1:0] bits correspondingly.
Either the DivN Divider or the Lock 8k Divider can be used or both
can be bypassed, as determined by the DIRECT_DIV bit and the
LOCK_8K bit.
When the DivN Divider is used for INn (3
≤
n
≤
14), the division factor
setting should observe the following order:
1. Select an input clock by the PRE_DIV_CH_VALUE[3:0] bits;
2. Write the lower eight bits of the division factor to the
PRE_DIVN_VALUE[7:0] bits;
3. Write the higher eight bits of the division factor to the
PRE_DIVN_VALUE[14:8] bits.
Once the division factor is set for the input clock selected by the
PRE_DIV_CH_VALUE[3:0] bits, it is valid until a different division factor
is set for the same input clock. The division factor is calculated as fol-
lows:
Division Factor = (the frequency of the clock input to the DivN
Divider ÷ the frequency of the DPLL required clock set by the
IN_FREQ[3:0] bits) - 1
The DivN Divider can only divide the input clock whose frequency is
lower than (
<
) 155.52 MHz.
When the Lock 8k Divider is used, the input clock is divided down to
8 kHz automatically.
The Pre-Divider configuration and the division factor setting depend
on the input clock on one of the IN3 ~ IN14 pins and the DPLL required
clock. Here is an example:
The input clock on the IN6 pin is 622.08 MHz; the DPLL required
clock is 6.48 MHz by programming the IN_FREQ[3:0] bits of register IN6
to ‘0010’. Do the following step by step to divide the input clock:
1. Use the HF Divider to divide the clock down to 155.52 MHz:
622.08 ÷ 155.52 = 4, so set the IN6_DIV[1:0] bits to ‘01’;
2. Use the DivN Divider to divide the clock down to 6.48 MHz:
Set the PRE_DIV_CH_VALUE[3:0] bits to ‘0110’;
Set the DIRECT_DIV bit in Register IN6_CNFG to ‘1’ and the
LOCK_8K bit in Register IN6_CNFG to ‘0’;
155.52 ÷ 6.48 = 24; 24 - 1 = 23, so set the
PRE_DIVN_VALUE[14:0] bits to ‘10111’.
Figure 3. Pre-Divider for An Input Clock
Input Clock INn
(14>n>3)
DivN Divider
Lock 8k Divider
HF Divider
(for IN5 & IN6 only)
Pre-Divider
IN5_DIV[1:0] bits / IN6_DIV[1:0] bits
DIRECT_DIV bit
LOCK_8K bit
DPLL required clock
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|---|---|
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