參數(shù)資料
型號: IDT82V3288
廠商: Integrated Device Technology, Inc.
英文描述: WAN PLL
中文描述: 廣域網(wǎng)鎖相環(huán)
文件頁數(shù): 151/170頁
文件大小: 1053K
代理商: IDT82V3288
IDT82V3288
WAN PLL
Programming Information
151
June 22, 2006
SYNC_PHASE_CNFG - Sync Phase Configuration
Address:7DH
Type: Read / Write
Default Value: XX000000
Bit
Name
Description
7 - 6
-
Reserved.
These bits set the sampling of EX_SYNC3 when EX_SYNC3 is enabled to synchronize the frame sync output signal. Nomi-
nally, the falling edge of EX_SYNC3 is aligned with the rising edge of the T0 selected input clock.
00: On target. (default)
01: 0.5 UI early.
10: 1 UI late.
11: 0.5 UI late.
These bits set the sampling of EX_SYNC2 when EX_SYNC2 is enabled to synchronize the frame sync output signal. Nomi-
nally, the falling edge of EX_SYNC2 is aligned with the rising edge of the T0 selected input clock.
00: On target. (default)
01: 0.5 UI early.
10: 1 UI late.
11: 0.5 UI late.
These bits set the sampling of EX_SYNC1 when EX_SYNC1 is enabled to synchronize the frame sync output signal. Nomi-
nally, the falling edge of EX_SYNC1 is aligned with the rising edge of the T0 selected input clock.
00: On target. (default)
01: 0.5 UI early.
10: 1 UI late.
11: 0.5 UI late.
5 - 4
SYNC_PH3[1:0]
3 - 2
SYNC_PH2[1:0]
1 - 0
SYNC_PH1[1:0]
7
6
5
4
3
2
1
0
-
-
SYNC_PH31
SYNC_PH30
SYNC_PH21
SYNC_PH20
SYNC_PH11
SYNC_PH10
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