參數(shù)資料
型號： IDT82V3288
廠商： Integrated Device Technology, Inc.
英文描述： WAN PLL
中文描述： 廣域網(wǎng)鎖相環(huán)
文件頁數(shù)： 25/170頁
文件大小： 1053K
代理商： IDT82V3288
IDT82V3288
WAN PLL
Functional Description
25
June 22, 2006
3.5.3
FREQUENCY MONITORING
Frequency is monitored by comparing the input clock with a refer-
ence clock. The reference clock can be derived from the master clock or
the output of T0 DPLL, as determined by the FREQ_MON_CLK bit.
A frequency hard alarm threshold is set for frequency monitoring. If
the FREQ_MON_HARD_EN bit is ‘1’, a frequency hard alarm is raised
when the frequency of the input clock with respect to the reference clock
is above the threshold; the alarm is cleared when the frequency is below
the threshold.
The frequency hard alarm threshold can be calculated as follows:
Frequency Hard Alarm Threshold (ppm) = (ALL_FREQ_HARD_
THRESHOLD[3:0] + 1) X FREQ_MON_FACTOR[3:0]
If the FREQ_MON_HARD_EN bit is ‘1’, the frequency hard alarm
status of the input clock is indicated by the INn_FREQ_HARD_ALARM
bit (14
≥
n
≥
1). When the FREQ_MON_HARD_EN bit is ‘0’, no fre-
quency hard alarm is raised even if the input clock is above the fre-
quency hard alarm threshold.
The input clock with a frequency hard alarm is disqualified for clock
selection for T0/T4 DPLL.
In addition, if the input clock is 2 kHz, 4 kHz or 8 kHz, its clock edges
with respect to the reference clock are monitored. If any edge drifts out-
side ±5%, the input clock is disqualified for clock selection for T0/T4
DPLL. The input clock is qualified if any edge drifts inside ±5%. This
function is supported only when the IN_NOISE_WINDOW bit is ‘1’.
The frequency of each input clock with respect to the reference clock
can be read by doing the following step by step:
1. Select an input clock by setting the IN_FREQ_READ_CH[3:0]
bits;
2. Read the value in the IN_FREQ_VALUE[7:0] bits and calculate
as follows:
Input Clock Frequency (ppm) = IN_FREQ_VALUE[7:0] X
FREQ_MON_FACTOR[3:0]
Note that the value set by the FREQ_MON_FACTOR[3:0] bits
depends on the application.
Table 5: Related Bit / Register in Chapter 3.5
Bit
Register
Address (Hex)
AMI1_LOS
1
AMI2_LOS
1
AMI1_LOS
2
AMI2_LOS
2
INTERRUPTS3_STS
0F
INTERRUPTS3_ENABLE_CNFG
12
BUCKET_SIZE_n_DATA[7:0] (3
≥
n
≥
0)
UPPER_THRESHOLD_n_DATA[7:0] (3
≥
n
≥
0)
LOWER_THRESHOLD_n_DATA[7:0] (3
≥
n
≥
0)
DECAY_RATE_n_DATA[1:0] (3
≥
n
≥
0)
BUCKET_SEL[1:0]
INn_NO_ACTIVITY_ALARM (14
≥
n
≥
1)
INn_FREQ_HARD_ALARM (14
≥
n
≥
1)
FREQ_MON_CLK
FREQ_MON_HARD_EN
ALL_FREQ_HARD_THRESHOLD[3:0]
FREQ_MON_FACTOR[3:0]
IN_NOISE_WINDOW
IN_FREQ_READ_CH[3:0]
IN_FREQ_VALUE[7:0]
BUCKET_SIZE_0_CNFG ~ BUCKET_SIZE_3_CNFG
UPPER_THRESHOLD_0_CNFG ~ UPPER_THRESHOLD_3_CNFG
LOWER_THRESHOLD_0_CNFG ~ LOWER_THRESHOLD_3_CNFG
DECAY_RATE_0_CNFG ~ DECAY_RATE_3_CNFG
IN1_CNFG ~ IN14_CNFG
33, 37, 3B, 3F
31, 35, 39, 3D
32, 36, 3A, 3E
34, 38, 3C, 40
14 ~ 17, 19 ~ 22
IN1_IN2_STS ~ IN13_IN14_STS
43 ~ 49
MON_SW_PBO_CNFG
0B
ALL_FREQ_MON_THRESHOLD_CNFG
FREQ_MON_FACTOR_CNFG
PHASE_MON_PBO_CNFG
IN_FREQ_READ_CH_CNFG
IN_FREQ_READ_STS
2F
2E
78
41
42
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