參數(shù)資料
型號(hào)： IDT82P2821BH
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 95/151頁
文件大?。?/td> 0K
描述： IC LIU T1/J1/E1 21+1CH 640-PBGA
標(biāo)準(zhǔn)包裝： 5
功能： 線路接口單元（LIU）
接口： E1，J1，T1
電路數(shù)： 1
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 640-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 640-PBGA-EP（31x31）
包裝： 托盤
包括： 缺陷和警報(bào)檢測，驅(qū)動(dòng)器過流檢測和保護(hù)，LLOS 檢測，PRBSARB / IB 檢測和生成
其它名稱： 82P2821BH
IDT82P2821
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Functional Description
48
February 6, 2009
3.5.5
PRBS, QRSS, ARB AND IB PATTERN GENERATION AND
DETECTION
The pattern includes: Pseudo Random Bit Sequence (PRBS), Quasi-
Random Signal Source (QRSS), Arbitrary Pattern (ARB) and Inband
Loopback (IB).
3.5.5.1 Pattern Generation
The pattern can be generated in the receive path or the transmit
path, as selected by the PG_POS bit (b3, PG,...).
The pattern to be generated is selected by the PG_EN[1:0] bits
(b5~4, PG,...).
If PRBS is selected, three kinds of PRBS patterns with maximum
zero restriction according to ITU-T O.151 and AT&T TR62411 are
provided. They are: (2^20 - 1) QRSS per O.150-4.5, (2^15 - 1) PRBS
per O.152 and (2^11 - 1) PRBS per O.150, as selected by the
PRBG_SEL[1:0] bits (b1~0, PG,...).
If ARB is selected, the content is programmed in the ARB[23:0] bits
If IB is selected, the IB generation is in compliance with ANSI T1.403.
The length of the IB code can be 3 to 8 bits, as determined by the
IBGL[1:0] bits (b5~4, IBL,...). The content is programmed in the IBG[7:0]
bits (b7~0, IBG,...).
The selected pattern is transmitted repeatedly until the PG_EN[1:0]
bits (b5~4, PG,...) is set to ‘00’.
When pattern is generated in the receive path, the reference clock is
XCLK or the recovered clock from the received signal, as selected by
the PG_CK bit (b6, PG,...). The selected reference clock is also output
on RCLKn (if available).
When pattern is generated in the transmit path, the reference clock is
XCLK1 or the transmit clock, as selected by the PG_CK bit (b6, PG,...).
The transmit clock refers to the clock input on TCLKn (in Transmit Single
Rail NRZ Format mode and in Transmit Dual Rail NRZ Format mode) or
the clock recovered from the data input on TDPn and TDNn (in Transmit
Dual Rail RZ Format mode).
In summary, do the followings step by step to generate pattern:
Select the generation direction by the PG_POS bit (b3, PG,...);
Select the reference clock by the PG_CK bit (b6, PG,...);
Select the PRBS pattern by the PRBG_SEL[1:0] bits (b1~0, PG,...)
when PRBS is to be generated; program the ARB pattern in the
ARB[23:0] bits (b7~0, ARBH~ARBM~ARBL,...) when ARB is to be
generated; or set the length and the content of the IB code in the
IBGL[1:0] bits (b5~4, IBL,...) and in the IBG[7:0] bits (b7~0, IBG,...)
respectively when IB is to be generated;
Set the PG_EN[1:0] bits (b5~4, PG,...) to generate the pattern.
If PRBS or ARB is selected to be generated, the following two steps
can be optionally implemented after the pattern is generated:
Insert a single bit error by writing ‘1’ to the ERR_INS bit (b5,
Invert the generated pattern by setting the PAG_INV bit (b2,
If pattern is generated in the receive path, the generated pattern
should be encoded by using AMI or B8ZS (for T1/J1) / HDB3 (for E1) in
Receive Dual Rail NRZ Format mode, Receive Dual Rail RZ Format
mode and Receive Dual Rail Sliced mode. The encoding rule is selected
by the R_CODE bit (b2, RCF1,...).
If pattern is generated in the transmit path, the generated pattern
should be encoded by using AMI or B8ZS (for T1/J1) / HDB3 (for E1).
The encoding rule is selected by the T_CODE bit (b2, TCF1,...).
The pattern generation is shown in Figure-26 and Figure-27.
Figure-26 Pattern Generation (1)
Figure-27 Pattern Generation (2)
The priority of pattern generation is higher than that of AIS genera-
tion. If they are generated in the same direction, the generated pattern
will overwrite the generated AIS.
1. XCLK is derived from MCLK. It is 1.544 MHz in T1/J1 mode or 2.048 MHz
in E1 mode.
PRBS/ARB/IB
pattern generator
PG_POS
CHn
TDPn/TDNn/TCLKn
RDPn/RDNn/RCLKn
TTIPn/TRINGn
RTIPn/RRINGn
XCLK
PG_EN[1:0]
TCLK/RCLK
PG_CK
PRBS generation
2^11-1
2^15-1
2^20-1
invert
ERR_INS
PAG_INV
Single bit error
insert
24 bits ARB
ARB[23:0]
PG_EN[1:0]
PRBG_SEL[1:0]
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