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參數(shù)資料
| 型號： | IDT82P2821BH |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 91/151頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/J1/E1 21+1CH 640-PBGA |
| 標準包裝： | 5 |
| 功能： | 線路接口單元（LIU） |
| 接口： | E1，J1，T1 |
| 電路數(shù)： | 1 |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 640-BGA 裸露焊盤 |
| 供應商設備封裝： | 640-PBGA-EP（31x31） |
| 包裝： | 托盤 |
| 包括： | 缺陷和警報檢測，驅動器過流檢測和保護，LLOS 檢測，PRBSARB / IB 檢測和生成 |
| 其它名稱： | 82P2821BH |
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IDT82P2821
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Functional Description
44
February 6, 2009
3.5.3
LOSS OF SIGNAL (LOS) DETECTION
The IDT82P2821 detects three kinds of LOS:
LLOS: Line LOS, detected in the receive path;
SLOS: System LOS, detected in the transmit system side;
TLOS: Transmit LOS, detected in the transmit line side.
3.5.3.1 Line LOS (LLOS)
The amplitude and density of the data received from the line side are
monitored. When the amplitude of the data is less than Q Vpp for N
consecutive pulse intervals, LLOS is declared. When the amplitude of
the data is more than P Vpp and the average density of marks is at least
12.5% for M consecutive pulse intervals starting with a mark, LLOS is
cleared. Here Q is defined by the ALOS[2:0] bits (b6~4, LOS,...). P is the
sum of Q and 250 mVpp. N and M are defined by the LAC bit (b7,
In T1/J1 mode, LLOS detection supports ANSI T1.231 and I.431. In
E1 mode, LLOS detection supports G.775 and ETSI 300233/I.431. The
criteria are selected by the LAC bit (b7, LOS,...).
When LLOS is detected, the LLOS_S bit (b0, STAT0,...) will be set. A
transition from ‘0’ to ‘1’ on the LLOS_S bit (b0, STAT0,...) or any transi-
tion (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the LLOS_S bit (b0, STAT0,...) will
set the LLOS_IS bit (b0, INTS0,...) to ‘1’, as selected by the LOS_IES bit
(b1, INTES,...). When the LLOS_IS bit (b0, INTS0,...) is ‘1’, an interrupt
will be reported by INT if not masked by the LLOS_IM bit (b0, INTM0,...).
Two pins (LLOS0 and LLOS) are dedicated to LLOS indication.
Whether LLOS is detected in channel 0 or not, LLOS0 is high for a
CLKE1 clock cycle to indicate the channel 0 position on LLOS. LLOS
indicates LLOS status of all 22 channels in a serial format and repeats
every 22 cycles. Refer to Figure-24. LLOS0 and LLOS are updated on
the rising edge of CLKE1. When the clock output on CLKE1 is disabled,
LLOS0 and LLOS will be held in High-Z state. The output on CLKE1 is
controlled by the CLKE1_EN bit (b3, CLKG) and the CLKE1 bit (b2,
CLKG). Refer to section 8.11 on page 132 for CLKE1 timing characteris-
tics.
LLOS may be counted by an internal Error Counter or may be indi-
cated by the RMFn pin. Refer to Section 3.5.6 Error Counter and
Section 3.5.7.1 RMFn Indication respectively.
During LLOS, in Receive Single Rail NRZ Format mode, Receive
Dual Rail NRZ Format mode and Receive Dual Rail RZ Format mode,
RDn and RDPn/RDNn output low level. In Receive Dual Rail Sliced
mode RDPn/RDNn still output sliced data. RCLKn (if available) outputs
During LLOS, if any of AIS, pattern generation in the receive path or
Digital Loopback is enabled, RDn, RDPn/RDNn and RCLKn output
corresponding data and clock, and the setting of the RCKH bit (b7,
RCF0,...) is ignored. Refer to the corresponding chapters for details.
Figure-24 LLOS Indication on Pins
1. XCLK is derived from MCLK. It is 1.544 MHz in T1/J1 mode or 2.048 MHz
in E1 mode.
Table-17 LLOS Criteria
Operation
Mode
LAC
Criteria
LLOS Declaring
LLOS Clearing
T1/J1
0
ANSI T1.231
below Q Vpp, N = 175 bits above P Vpp, 12.5% mark density with less than 100 consecutive zeros, M = 175 bits
1
ANSI I.431
below Q Vpp, N = 1544 bits above P Vpp, 12.5% mark density with less than 100 consecutive zeros, M = 175 bits
E1
0
G.775
below Q Vpp, N = 32 bits
above P Vpp, 12.5% mark density with less than 16 consecutive zeros, M = 32 bits
1
ETSI 300233/
I.431
below Q Vpp, N = 2048 bits
above P Vpp, 12.5% mark density with less than 16 consecutive zeros, M = 32 bits
One LLOS Indication Cycle
LLOS
LLOS0
CLKE1
CH0 CH1 CH2
CH21 CH0
01
2
21
0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82P2821BHG | 功能描述:IC LINE INTERFACE UNIT 640-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS 產品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
| IDT82P2828 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:28(+1) Channel High-Density T1/E1/J1 Line Interface Unit |
| IDT82P2828BH | 功能描述:IC LIU T1/J1/E1 28+1CH 640-PBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82P2828BHG | 功能描述:IC LIU T1/J1/E1 28+1CH 640-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82P2916 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:16-Channel High-Density T1/E1/J1 Line Interface Unit |
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